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Port details
chipvault Project organizer for VHDL and Verilog RTL hardware designs
200607 cad on this many watch lists=2 search for ports that depend on this port Find issues related to this port Report an issue related to this port

There is no maintainer for this port.
Any concerns regarding this port should be directed to the FreeBSD Ports mailing list via ports@FreeBSD.org search for ports maintained by this maintainer
Port Added: 29 Jan 2003 03:46:10
License: not specified in port
ChipVault is a VHDL and Verilog Chip Design Organization tool which improves
design efficiency by:
   - Providing the ability to Navigate and Edit files Hierarchically.
   - Automatically generating Schematic Component Port views of VHDL and
     Verilog RTL files.
   - Automating RTL instantiation and template generation.
   - Providing Revision Control (designed for HW, not SW development).
   - Supporting External Tool Hooks (bottom-up vcoms,etc).
   - Providing an Issue Tracking Log with sorting.
   - Providing Netlist sorting and hierarchy viewing.
   - Supporting web-sharing of RTL files (both encrypted and clear).
   - Fast and Nimble.

WWW: http://chipvault.sourceforge.net/
SVNWeb : Homepage : PortsMon

To install the port: cd /usr/ports/cad/chipvault/ && make install clean
To add the package: pkg install chipvault

PKGNAME: chipvault


NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.

Runtime dependencies:
  1. perl5.20.2 : lang/perl5.20
There are no ports dependent upon this port

Configuration Options
     No options to configure

USES:
perl5 shebangfix

Master Sites:
  1. http://chipvault.sourceforge.net/
  2. http://distcache.FreeBSD.org/ports-distfiles/

Number of commits found: 10

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
20 Jan 2014 20:30:19
Original commit files touched by this commit  200607
Revision:340465
antoine search for other commits by this committer
Stage support
20 Sep 2013 15:58:42
Original commit files touched by this commit  200607
Revision:327711
bapt search for other commits by this committer
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
03 Aug 2013 13:44:01
Original commit files touched by this commit  200607
Revision:324191  Sanity Test Failure
mat search for other commits by this committer
- Convert to new perl framework
- Remove MAKE_JOBS_SAFE=yes, it's the default.
20 Mar 2011 12:54:45
Original commit files touched by this commit  200607
miwi search for other commits by this committer
- Get Rid MD5 support
20 Jul 2006 07:45:16
Original commit files touched by this commit  200607
erwin search for other commits by this committer
Update to 200607

PR:             100593
Submitted by:   Soeren Straarup <xride@x12.dk>
24 Nov 2005 00:22:47
Original commit files touched by this commit  200211
pav search for other commits by this committer
- Add SHA256
05 Feb 2004 20:38:07
Original commit files touched by this commit  200211
trevor search for other commits by this committer
Use PLIST_FILES.

Reviewed by:    marcus
27 Jan 2004 20:51:07
Original commit files touched by this commit  200211
trevor search for other commits by this committer
Add SIZE.
20 Feb 2003 16:52:46
Original commit files touched by this commit  200211
knu search for other commits by this committer
De-pkg-comment.
29 Jan 2003 03:45:13
Original commit files touched by this commit  200211
ijliao search for other commits by this committer
add chipvault 200211
A project organizer for VHDL and Verilog RTL hardware designs

Number of commits found: 10

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