| Commit History - (may be incomplete: see CVSWeb link above for full details) |
| Date | By | Description |
16 Jun 2011 10:41:31
  2.12.a
|
bapt  |
Point to the new home
Make it fetchable again |
20 Mar 2011 12:54:45
2.12.a
|
miwi |
- Get Rid MD5 support |
27 Oct 2008 15:59:27
2.12.a
|
tabthorpe |
- Reassign to ports |
23 Aug 2007 04:00:04
2.12.a
|
tabthorpe |
- change maintainer address on ports I maintain
Approved by: clsung (mentor) |
21 Jul 2007 01:21:52
2.12.a
|
ijliao |
'actually' pass maintainership |
21 Jul 2007 01:20:50
2.12.a
|
ijliao |
upgrade to 2.12.a
pass maintainership to submitter
PR: 114768
Submitted by: Thomas Abthorpe <thomas@goodking.ca> |
03 Aug 2006 03:26:38
2.11.a
|
clsung |
- maintainer is a committer |
20 Jan 2006 14:18:34
2.11.a
|
arved |
Fix build on sparc |
19 Jan 2006 23:31:12
2.11.a
|
kris |
BROKEN on sparc64: Does not compile |
04 Jan 2006 05:56:54
2.11.a
|
edwin |
Fix maintainership (set to submitter) |
29 Dec 2005 03:48:58
2.11.a
|
edwin |
[NEW PORT] cad/gplcver: A Verilog HDL simulator
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw> |
