Number of commits found: 10

Point to the new home
Make it fetchable again

- Reassign to ports

- change maintainer address on ports I maintain

Approved by:    clsung (mentor)

'actually' pass maintainership

upgrade to 2.12.a
pass maintainership to submitter

PR:             114768
Submitted by:   Thomas Abthorpe <thomas@goodking.ca>

- maintainer is a committer

Fix build on sparc

BROKEN on sparc64: Does not compile

Fix maintainership (set to submitter)

[NEW PORT] cad/gplcver: A Verilog HDL simulator

        GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
        It also implements some of the 2001 P1364 standard features
        including all three PLI interfaces (tf_, acc_ and vpi_) as
        defined in the 2001 Language Reference Manual (LRM).

        Verilog is the name for both a language for describing
        electronic hardware called a hardware description language
        (HDL) and the name of the program that simulates HDL circuit
        descriptions to verify that described circuits will function
        correctly when the are constructed. Verilog is used only
        for describing digital logic circuits. Other HDLs such as
        Spice are used for describing analog circuits. There is an
        IEEE standard named P1364 that standardizes the Verilog HDL
        and the behavior of Verilog simulators.  Verilog is officially
        defined in the IEEE P1364 Language Reference Manual (LRM)
        that can be purchased from IEEE. There are many good books
        for learning that teach the Verilog HDL and/or that teach
        digital circuit design using Verilog.

        WWW: http://www.pragmatic-c.com/gpl-cver/

PR:             ports/80968
Submitted by:   Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>

Number of commits found: 10

12 vulnerabilities affecting 17 ports have been reported in the past 14 days

^* - modified, not new

All vulnerabilities