Number of commits found: 21

- Update to version 0.9.5
- Add LICENSE
- Update project homepage

PR:             ports/162280
Submitted by:   Niclas Zeising <niclas.zeising@gmail.com> (maintainer)

- Update to version 0.9.4
- Give maintainership to submitter

PR:             ports/162069
Submitted by:   Niclas Zeising <niclas.zeising@gmail.com>

- Get Rid MD5 support

- Update to 0.9.2.

- Update to 0.9.1.

- Update to 0.8.7.

- Update 0.8.6.

- Update to 0.8.5.

- Update to 0.8.4.

- Update to 0.8.3

- Update to 0.8.2
- Fix compiling with gcc 4.1
- Change my email

Approved by:    sem (mentor)

Update to 0.8.1
Add second MASTER_SITES
Add SHA256

PR:             88749
Submitted by:   Joachim Strombergson <watchman@ludd.ltu.se> (maintainer)

Update to 0.8

PR:             72949
Submitted by:   Joachim Strombergson <watchman@ludd.ltu.se>

Update to 0.7.20040606.

PR:             ports/68643
Submitted by:   maintainer

- Update to version 20040220

PR:             ports/64432
Submitted by:   maintainer

Update to 20031202 snapshot.  Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt:

Combination 64bit/32bit runtime support now works fully on AMD64
systems; wait on lists of named events now works; there is no
longer a common iverilog.conf, instead there are target specific
foo.conf files with a new and cleaner format; 64bit values are more
portably handled; several synthesis bugs related to the control inputs
of flip-flops have been fixed.

Committer is marking this BROKEN on 4.x while we investigate install
problems.  It works on 5.x only for now.

PR:             ports/60162
Submitted by:   Joachim Strombergson <watchman@ludd.luth.se> (maintainer)

Maintainer Update to latest snapshot.  Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320

Maintainer update to snapshot version.  In addition to fixing the port
for gcc3.3, 10 months of updates are included:

- Rework expression parsing and elaboration to accomodate real/realtime
values and expressions.
- Calculate delay statement delays using elaborated expressions instead
of pre-elaborated expression trees.
- Implement the wait statement behaviorally instead of as nets.
- Support event names as expression elements.
- Fix configuration errors, spelling errors, clarification of certain
objects.

See internal revision logs in each file for more elaboration.

Update to iverilog 0.7

Submitted by:    Joachim Str?mbergson <watchman@ludd.luth.se>

Update to 0.6 after my long absence    

add iverilog, a Verilog simulation and synthesis tool    

Number of commits found: 21

12 vulnerabilities affecting 17 ports have been reported in the past 14 days

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