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non port: head/cad/logisim/Makefile
SVNWeb

Number of commits found: 4

Sat, 20 Dec 2014
[ 17:28 bapt ] Original commit   Revision:375015
375015 cad/logisim/Makefile
Cleanup plist
Sun, 1 Jun 2014
[ 14:46 ohauer ] Original commit   Revision:356129
356129 cad/logisim/Makefile
- add stage support
Fri, 20 Sep 2013
[ 15:58 bapt ] Original commit   Revision:327711
327711 cad/admesh/Makefile
327711 cad/adms/Makefile
327711 cad/alliance/Makefile
327711 cad/astk-client/Makefile
327711 cad/astk-serveur/Makefile
327711 cad/atlc/Makefile
327711 cad/basicdsp/Makefile
327711 cad/brlcad/Makefile
327711 cad/calculix/Makefile
327711 cad/cascade/Makefile

(Only the first 10 of 103 ports in this commit are shown above. View all ports for this commit)
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
Sat, 2 Mar 2013
[ 13:26 pawel ] Original commit   Revision:313229
313229 cad/Makefile
313229 cad/logisim
313229 cad/logisim/Makefile
313229 cad/logisim/distinfo
313229 cad/logisim/pkg-descr
Logisim is an educational tool for designing and simulating digital logic
circuits. With its simple toolbar interface and simulation of circuits as
you build them, it is simple enough to facilitate learning the most basic
concepts related to logic circuits. With the capacity to build larger circuits
from smaller subcircuits, and to draw bundles of wires with a single mouse
drag, Logisim can be used (and is used) to design and simulate entire CPUs for
educational purposes.

Logisim is used by students at colleges and universities around the world in
many types of classes, ranging from a brief unit on logic in general-education
computer science surveys, to computer organization courses, to full-semester
courses on computer architecture.

WWW: http://ozark.hendrix.edu/~burch/logisim/

PR:		ports/176354
Submitted by:	Javad Kouhi <javad.kouhi@gmail.com>

Number of commits found: 4

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