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Port details
p5-Verilog-Perl 3.223 cad on this many watch lists=0 search for ports that depend on this port
Building point for Verilog support in the Perl language
Maintained by: otacilio.neto@ee.ufcg.edu.br search for ports maintained by this maintainer
Port Added: 26 May 2009 12:01:59
Also Listed In: perl5


The Verilog-Perl library is a building point for Verilog support in the Perl 
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows 
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading 
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across 
  multiple files. Vrename uses a simple and efficient three step process. 
  First, you run vrename to create a list of signals in the design. You then 
  edit this list, changing as many symbols as you wish. Vrename is then run a 
  second time to apply the changes.

WWW:	http://www.veripool.org/wiki/verilog-perl
CVSWeb : Sources : Main Web Site : Distfiles Availability : PortsMon
Required To Build: textproc/flex, devel/gmake, devel/bison, lang/perl5.8
Required To Run: lang/perl5.8

To install the port: cd /usr/ports/cad/p5-Verilog-Perl/ && make install clean
To add the package: pkg_add -r p5-Verilog-Perl


Configuration Options
     No options to configure

Master Sites:
ftp://ftp.funet.fi/pub/languages/perl/CPAN/modules/by-module/Verilog/
ftp://ftp.cpan.org/pub/CPAN/modules/by-module/Verilog/
http://www.cpan.dk/modules/by-module/Verilog/
http://ring.nict.go.jp/archives/lang/perl/CPAN/modules/by-module/Verilog/
http://ring.k-opti.com/archives/lang/perl/CPAN/modules/by-module/Verilog/
http://ring.riken.jp/archives/lang/perl/CPAN/modules/by-module/Verilog/
ftp://ftp.kddlabs.co.jp/lang/perl/CPAN/modules/by-module/Verilog/
ftp://ftp.dti.ad.jp/pub/lang/CPAN/modules/by-module/Verilog/
ftp://ftp.sunet.se/pub/lang/perl/CPAN/modules/by-module/Verilog/
ftp://mirror.hiwaay.net/CPAN/modules/by-module/Verilog/
ftp://ftp.mirrorservice.org/sites/ftp.funet.fi/pub/languages/perl/CPAN/modules/by-module/Verilog/
ftp://csociety-ftp.ecn.purdue.edu/pub/CPAN/modules/by-module/Verilog/
ftp://ftp.isu.net.sa/pub/CPAN/modules/by-module/Verilog/
ftp://ftp.cs.colorado.edu/pub/perl/CPAN/modules/by-module/Verilog/
ftp://cpan.pop-mg.com.br/pub/CPAN/modules/by-module/Verilog/
http://at.cpan.org/modules/by-module/Verilog/
ftp://ftp.chg.ru/pub/lang/perl/CPAN/modules/by-module/Verilog/
ftp://ftp.auckland.ac.nz/pub/perl/CPAN/modules/by-module/Verilog/
http://backpan.cpan.org/modules/by-module/Verilog/
ftp://ftp.FreeBSD.org/pub/FreeBSD/ports/distfiles/

Number of commits found: 9

Commit History - (may be incomplete: see CVSWeb link above for full details)
DateByDescription
18 Jan 2010 00:57:34
Original commit files touched by this commit  3.223
pgollucci search for other commits by this committer
- Update to 3.223

PR:             ports/142626
Submitted by:   myself (pgollucci@)
Approved by:    otacilio.neto@ee.ufcg.edu.br (maintainer)
27 Dec 2009 02:02:02
Original commit files touched by this commit  3.222
pgollucci search for other commits by this committer
- Update to 3.222

PR:             ports/141552
Approved by:    maintainer
Submitted by:   myself (pgollucci@)
04 Nov 2009 15:43:10
Original commit files touched by this commit  3.221
miwi search for other commits by this committer
- Update to 3.221

PR:             140231
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)
15 Sep 2009 14:16:14
Original commit files touched by this commit  3.212
az search for other commits by this committer
- Fix compile problem with over optimization caused by -O2 flag for gcc in base
 prior OSVERSION 700042
- Unbreak

Approved by:    portmgr (miwi)
Feature safe:   yes
14 Sep 2009 07:58:47
Original commit files touched by this commit  3.212
miwi search for other commits by this committer
- mark BROKEN does not compile
24 Aug 2009 07:01:24
Original commit files touched by this commit  3.212
az search for other commits by this committer
Update to 2.213

PR:     ports/138081
Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)
15 Jul 2009 01:42:29
Original commit files touched by this commit  3.211
pgollucci search for other commits by this committer
- Update to 2.11

PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)
26 May 2009 12:54:56
Original commit files touched by this commit  3.210
garga search for other commits by this committer
- Add missing dependency (bison)

Reported by:    QAT
Pointyhat to:   garga
26 May 2009 12:01:39
Original commit files touched by this commit  3.210
garga search for other commits by this committer
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>

Number of commits found: 9

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