| Commit History - (may be incomplete: see CVSWeb link above for full details) |
| Date | By | Description |
18 Jan 2010 00:57:34
3.223
|
pgollucci  |
- Update to 3.223
PR: ports/142626
Submitted by: myself (pgollucci@)
Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer) |
27 Dec 2009 02:02:02
3.222
|
pgollucci  |
- Update to 3.222
PR: ports/141552
Approved by: maintainer
Submitted by: myself (pgollucci@) |
04 Nov 2009 15:43:10
3.221
|
miwi  |
- Update to 3.221
PR: 140231
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer) |
15 Sep 2009 14:16:14
3.212
|
az  |
- Fix compile problem with over optimization caused by -O2 flag for gcc in base
prior OSVERSION 700042
- Unbreak
Approved by: portmgr (miwi)
Feature safe: yes |
14 Sep 2009 07:58:47
3.212
|
miwi  |
- mark BROKEN does not compile |
24 Aug 2009 07:01:24
3.212
|
az  |
Update to 2.213
PR: ports/138081
Submitted by: tacilio.net at ee.ufcg.edu.br (maintainer) |
15 Jul 2009 01:42:29
3.211
|
pgollucci  |
- Update to 2.11
PR: ports/136485
Submitted by: otacilio.neto@ee.ufcg.edu.br (maintainer) |
26 May 2009 12:54:56
3.210
|
garga  |
- Add missing dependency (bison)
Reported by: QAT
Pointyhat to: garga |
26 May 2009 12:01:39
3.210
|
garga  |
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
cross references and makes it easy to rename signal and module names across
multiple files. Vrename uses a simple and efficient three step process.
First, you run vrename to create a list of signals in the design. You then
edit this list, changing as many symbols as you wish. Vrename is then run a
second time to apply the changes.
WWW: http://www.veripool.org/wiki/verilog-perl
PR: ports/134124
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br> |