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non port: head/cad/p5-Verilog-Perl/Makefile
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Number of commits found: 15

Fri, 20 Sep 2013
[ 15:58 bapt ] Original commit 
327711 cad/admesh/Makefile
327711 cad/adms/Makefile
327711 cad/alliance/Makefile
327711 cad/astk-client/Makefile
327711 cad/astk-serveur/Makefile
327711 cad/atlc/Makefile
327711 cad/basicdsp/Makefile
327711 cad/brlcad/Makefile
327711 cad/calculix/Makefile
327711 cad/cascade/Makefile

(Only the first 10 of 103 ports in this commit are shown above. View all ports for this commit)
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
Tue, 17 Sep 2013
[ 06:12 bapt ] Original commit 
327450 cad/p5-Verilog-Perl/Makefile
327450 devel/abi-compliance-checker/Makefile
327450 devel/api-sanity-autotest/Makefile
327450 irc/kvirc/Makefile
327450 irc/znc/Makefile
327450 net-mgmt/nagios/Makefile
327450 net-mgmt/netxms/Makefile
327450 textproc/p5-Plagger/Makefile
Convert to new perl framework

Submitted by:	az
Fri, 3 May 2013
[ 21:42 rakuco ] Original commit 
317268 cad/p5-Verilog-Perl/Makefile
317268 cad/p5-Verilog-Perl/distinfo
Update to 3.400.

PR:		ports/177726
Submitted by:	Otacilio <otacilio.neto@ee.ufcg.edu.br> (maintainer)
Fri, 8 Mar 2013
[ 11:32 bapt ] Original commit 
313635 Mk/Uses/bison.mk
313635 audio/csound/Makefile
313635 audio/denemo/Makefile
313635 audio/rezound/Makefile
313635 audio/sfront/Makefile
313635 biology/chemeq/Makefile
313635 cad/alliance/Makefile
313635 cad/brlcad/Makefile
313635 cad/iverilog/Makefile
313635 cad/opencascade/Makefile

(Only the first 10 of 209 ports in this commit are shown above. View all ports for this commit)
Convert USE_BISON to USES= bison

It brings bison as a build dependency in case it is set the following way:
USES= bison or USES= bison:build

it brings bison as a run dependency in case it is set the following way:
USES= bison:run

it brings bison both as a run and build dependency in case it the set the
following way:
USES= bison:both

While here trim some headers
Convert some USE_GNOME= gnomehack to USES= pathfix
Mon, 27 Aug 2012
[ 21:49 swills ] Original commit 
303256 cad/p5-Verilog-Perl/Makefile
303256 cad/p5-Verilog-Perl/distinfo
- Update to 3.316

PR:		ports/171063
Approved by:	otacilio.neto@ee.ufcg.edu.br (maintainer)
Fri, 23 Jul 2010
[ 14:33 sylvio ] Original commit 
1.10 cad/p5-Verilog-Perl/Makefile
1.7 cad/p5-Verilog-Perl/distinfo
1.4 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.251

PR:             ports/148726
Submitted by:   Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)
Mon, 18 Jan 2010
[ 00:57 pgollucci ] Original commit 
1.9 cad/p5-Verilog-Perl/Makefile
1.6 cad/p5-Verilog-Perl/distinfo
- Update to 3.223

PR:             ports/142626
Submitted by:   myself (pgollucci@)
Approved by:    otacilio.neto@ee.ufcg.edu.br (maintainer)
Sun, 27 Dec 2009
[ 02:02 pgollucci ] Original commit 
1.8 cad/p5-Verilog-Perl/Makefile
1.5 cad/p5-Verilog-Perl/distinfo
- Update to 3.222

PR:             ports/141552
Approved by:    maintainer
Submitted by:   myself (pgollucci@)
Wed, 4 Nov 2009
[ 15:43 miwi ] Original commit 
1.7 cad/p5-Verilog-Perl/Makefile
1.4 cad/p5-Verilog-Perl/distinfo
1.3 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.221

PR:             140231
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)
Tue, 15 Sep 2009
[ 13:16 az ] Original commit 
1.6 cad/p5-Verilog-Perl/Makefile
- Fix compile problem with over optimization caused by -O2 flag for gcc in base
 prior OSVERSION 700042
- Unbreak

Approved by:    portmgr (miwi)
Feature safe:   yes
Mon, 14 Sep 2009
[ 06:58 miwi ] Original commit 
1.5 cad/p5-Verilog-Perl/Makefile
- mark BROKEN does not compile
Mon, 24 Aug 2009
[ 06:01 az ] Original commit 
1.4 cad/p5-Verilog-Perl/Makefile
1.3 cad/p5-Verilog-Perl/distinfo
Update to 2.213

PR:     ports/138081
Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)
Wed, 15 Jul 2009
[ 00:42 pgollucci ] Original commit 
1.3 cad/p5-Verilog-Perl/Makefile
1.2 cad/p5-Verilog-Perl/distinfo
1.2 cad/p5-Verilog-Perl/pkg-plist
- Update to 2.11

PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)
Tue, 26 May 2009
[ 11:54 garga ] Original commit 
1.2 cad/p5-Verilog-Perl/Makefile
- Add missing dependency (bison)

Reported by:    QAT
Pointyhat to:   garga
[ 11:01 garga ] Original commit 
1.108 cad/Makefile
1.1 cad/p5-Verilog-Perl/Makefile
1.1 cad/p5-Verilog-Perl/distinfo
1.1 cad/p5-Verilog-Perl/pkg-descr
1.1 cad/p5-Verilog-Perl/pkg-plist
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>

Number of commits found: 15

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