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I am looking for an LTO tape library. Do you have one to spare?
found something from the cache
non port: head/cad/p5-Verilog-Perl/distinfo
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Number of commits found: 11

Fri, 27 Jun 2014
[ 18:59 garga ] Original commit 
359597 cad/p5-Verilog-Perl/Makefile
359597 cad/p5-Verilog-Perl/distinfo
359597 cad/p5-Verilog-Perl/files
359597 cad/p5-Verilog-Perl/files/patch-Makefile.PL
359597 cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL
359597 cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
359597 cad/p5-Verilog-Perl/pkg-descr
359597 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.404
- Fix build, it needs gcc

PR:		191368
Submitted by:	otaciliodearaujo@gmail.com (maintainer)
Fri, 3 May 2013
[ 21:42 rakuco ] Original commit 
317268 cad/p5-Verilog-Perl/Makefile
317268 cad/p5-Verilog-Perl/distinfo
Update to 3.400.

PR:		ports/177726
Submitted by:	Otacilio <otacilio.neto@ee.ufcg.edu.br> (maintainer)
Mon, 27 Aug 2012
[ 21:49 swills ] Original commit 
303256 cad/p5-Verilog-Perl/Makefile
303256 cad/p5-Verilog-Perl/distinfo
- Update to 3.316

PR:		ports/171063
Approved by:	otacilio.neto@ee.ufcg.edu.br (maintainer)
Sun, 20 Mar 2011
[ 12:54 miwi ] Original commit 
1.4 cad/admesh/distinfo
1.6 cad/adms/distinfo
1.4 cad/atlc/distinfo
1.3 cad/basicdsp/distinfo
1.20 cad/calculix/distinfo
1.10 cad/chipmunk/distinfo
1.5 cad/chipvault/distinfo
1.5 cad/cider/distinfo
1.7 cad/dinotrace/distinfo
1.6 cad/dxf2fig/distinfo

(Only the first 10 of 3505 ports in this commit are shown above. View all ports for this commit)
- Get Rid MD5 support
Fri, 23 Jul 2010
[ 14:33 sylvio ] Original commit 
1.10 cad/p5-Verilog-Perl/Makefile
1.7 cad/p5-Verilog-Perl/distinfo
1.4 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.251

PR:             ports/148726
Submitted by:   Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)
Mon, 18 Jan 2010
[ 00:57 pgollucci ] Original commit 
1.9 cad/p5-Verilog-Perl/Makefile
1.6 cad/p5-Verilog-Perl/distinfo
- Update to 3.223

PR:             ports/142626
Submitted by:   myself (pgollucci@)
Approved by:    otacilio.neto@ee.ufcg.edu.br (maintainer)
Sun, 27 Dec 2009
[ 02:02 pgollucci ] Original commit 
1.8 cad/p5-Verilog-Perl/Makefile
1.5 cad/p5-Verilog-Perl/distinfo
- Update to 3.222

PR:             ports/141552
Approved by:    maintainer
Submitted by:   myself (pgollucci@)
Wed, 4 Nov 2009
[ 15:43 miwi ] Original commit 
1.7 cad/p5-Verilog-Perl/Makefile
1.4 cad/p5-Verilog-Perl/distinfo
1.3 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.221

PR:             140231
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)
Mon, 24 Aug 2009
[ 06:01 az ] Original commit 
1.4 cad/p5-Verilog-Perl/Makefile
1.3 cad/p5-Verilog-Perl/distinfo
Update to 2.213

PR:     ports/138081
Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)
Wed, 15 Jul 2009
[ 00:42 pgollucci ] Original commit 
1.3 cad/p5-Verilog-Perl/Makefile
1.2 cad/p5-Verilog-Perl/distinfo
1.2 cad/p5-Verilog-Perl/pkg-plist
- Update to 2.11

PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)
Tue, 26 May 2009
[ 11:01 garga ] Original commit 
1.108 cad/Makefile
1.1 cad/p5-Verilog-Perl/Makefile
1.1 cad/p5-Verilog-Perl/distinfo
1.1 cad/p5-Verilog-Perl/pkg-descr
1.1 cad/p5-Verilog-Perl/pkg-plist
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>

Number of commits found: 11

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