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Please give me your LTO-4 or better tape library and I'll put it to good use.
found something from the cache
non port: head/cad/p5-Verilog-Perl/pkg-descr
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Number of commits found: 2

Fri, 27 Jun 2014
[ 18:59 garga ] Original commit 
359597 cad/p5-Verilog-Perl/Makefile
359597 cad/p5-Verilog-Perl/distinfo
359597 cad/p5-Verilog-Perl/files
359597 cad/p5-Verilog-Perl/files/patch-Makefile.PL
359597 cad/p5-Verilog-Perl/files/patch-Parser__Makefile.PL
359597 cad/p5-Verilog-Perl/files/patch-Preproc__Makefile.PL
359597 cad/p5-Verilog-Perl/pkg-descr
359597 cad/p5-Verilog-Perl/pkg-plist
- Update to 3.404
- Fix build, it needs gcc

PR:		191368
Submitted by:	otaciliodearaujo@gmail.com (maintainer)
Tue, 26 May 2009
[ 11:01 garga ] Original commit 
1.108 cad/Makefile
1.1 cad/p5-Verilog-Perl/Makefile
1.1 cad/p5-Verilog-Perl/distinfo
1.1 cad/p5-Verilog-Perl/pkg-descr
1.1 cad/p5-Verilog-Perl/pkg-plist
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>

Number of commits found: 2

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