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non port: cad/gplcver/Makefile
SVNWeb

Number of commits found: 14

Mon, 9 Jun 2014
[ 11:21 olgeni ] Original commit   Revision:357139
357139 archivers/file-roller/Makefile
357139 astro/ephem/Makefile
357139 astro/gpsman/Makefile
357139 astro/josm/Makefile
357139 astro/p5-ZConf-Weather/Makefile
357139 astro/wmspaceweather/Makefile
357139 astro/xephem/Makefile
357139 audio/ampache/Makefile
357139 audio/beets/Makefile
357139 audio/cdparanoia/Makefile

(Only the first 10 of 120 ports in this commit are shown above. View all ports for this commit)
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.

CR:		D196
Approved by:	portmgr (bapt)
Sun, 1 Jun 2014
[ 14:48 ohauer ] Original commit   Revision:356131
356131 cad/atlc/Makefile
356131 cad/brlcad/Makefile
356131 cad/gplcver/Makefile
356131 cad/qfsm/Makefile
- USE_(BZIP2|XZ) -> USES=tar:(bzip2|xz)
Thu, 27 Feb 2014
[ 13:43 ehaupt ] Original commit   Revision:346330
346330 cad/gplcver/Makefile
Support staging
Fri, 20 Sep 2013
[ 15:58 bapt ] Original commit   Revision:327711
327711 cad/admesh/Makefile
327711 cad/adms/Makefile
327711 cad/alliance/Makefile
327711 cad/astk-client/Makefile
327711 cad/astk-serveur/Makefile
327711 cad/atlc/Makefile
327711 cad/basicdsp/Makefile
327711 cad/brlcad/Makefile
327711 cad/calculix/Makefile
327711 cad/cascade/Makefile

(Only the first 10 of 103 ports in this commit are shown above. View all ports for this commit)
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
Thu, 16 Jun 2011
[ 10:41 bapt ] Original commit 
1.10 cad/gplcver/Makefile
1.2 cad/gplcver/pkg-descr
Point to the new home
Make it fetchable again
Mon, 27 Oct 2008
[ 15:59 tabthorpe ] Original commit 
1.9 cad/gplcver/Makefile
1.25 devel/libcwd/Makefile
1.25 devel/pharmacy/Makefile
1.40 misc/kcd-devel/Makefile
1.40 misc/kcd/Makefile
1.22 x11-wm/sapphire/Makefile
- Reassign to ports
Thu, 23 Aug 2007
[ 04:00 tabthorpe ] Original commit 
1.4 archivers/p5-Compress-Raw-Bzip2/Makefile
1.6 archivers/p5-Compress-Raw-Zlib/Makefile
1.6 archivers/p5-IO-Compress-Base/Makefile
1.4 archivers/p5-IO-Compress-Bzip2/Makefile
1.8 cad/gplcver/Makefile
1.12 converters/p5-Convert-TNEF/Makefile
1.7 databases/mrtg-mysql-load/Makefile
1.31 databases/pear-DB/Makefile
1.16 deskutils/kompose/Makefile
1.29 devel/global/Makefile

(Only the first 10 of 58 ports in this commit are shown above. View all ports for this commit)
- change maintainer address on ports I maintain

Approved by:    clsung (mentor)
Sat, 21 Jul 2007
[ 01:21 ijliao ] Original commit 
1.7 cad/gplcver/Makefile
'actually' pass maintainership
[ 01:20 ijliao ] Original commit 
1.6 cad/gplcver/Makefile
1.2 cad/gplcver/distinfo
upgrade to 2.12.a
pass maintainership to submitter

PR:             114768
Submitted by:   Thomas Abthorpe <thomas@goodking.ca>
Thu, 3 Aug 2006
[ 03:26 clsung ] Original commit 
1.5 cad/gplcver/Makefile
- maintainer is a committer
Fri, 20 Jan 2006
[ 14:18 arved ] Original commit 
1.4 cad/gplcver/Makefile
1.1 cad/gplcver/files/patch-src-v.h
1.1 cad/gplcver/files/patch-src-v_dbg2.c
1.1 cad/gplcver/files/patch-src-v_ex2.c
1.1 cad/gplcver/files/patch-src-v_ms.c
1.1 cad/gplcver/files/patch-src-v_src3.c
Fix build on sparc
Thu, 19 Jan 2006
[ 23:31 kris ] Original commit 
1.3 cad/gplcver/Makefile
BROKEN on sparc64: Does not compile
Wed, 4 Jan 2006
[ 05:56 edwin ] Original commit 
1.2 cad/gplcver/Makefile
Fix maintainership (set to submitter)
Thu, 29 Dec 2005
[ 03:48 edwin ] Original commit 
1.80 cad/Makefile
1.1 cad/gplcver/Makefile
1.1 cad/gplcver/distinfo
1.1 cad/gplcver/pkg-descr
[NEW PORT] cad/gplcver: A Verilog HDL simulator

        GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
        It also implements some of the 2001 P1364 standard features
        including all three PLI interfaces (tf_, acc_ and vpi_) as
        defined in the 2001 Language Reference Manual (LRM).

        Verilog is the name for both a language for describing
        electronic hardware called a hardware description language
        (HDL) and the name of the program that simulates HDL circuit
        descriptions to verify that described circuits will function
        correctly when the are constructed. Verilog is used only
        for describing digital logic circuits. Other HDLs such as
        Spice are used for describing analog circuits. There is an
        IEEE standard named P1364 that standardizes the Verilog HDL
        and the behavior of Verilog simulators.  Verilog is officially
        defined in the IEEE P1364 Language Reference Manual (LRM)
        that can be purchased from IEEE. There are many good books
        for learning that teach the Verilog HDL and/or that teach
        digital circuit design using Verilog.

        WWW: http://www.pragmatic-c.com/gpl-cver/

PR:             ports/80968
Submitted by:   Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>

Number of commits found: 14

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