notbugAs an Amazon Associate I earn from qualifying purchases.
Want a good read? Try FreeBSD Mastery: Jails (IT Mastery Book 15)
Ukraine
non port: cad/gplcver/Makefile
SVNWeb

Number of commits found: 17

Tue, 6 Apr 2021
[ 14:31 Mathieu Arnold (mat) search for other commits by this committer ]    commit hash:305f148f482daf30dcf728039d03d019f88344eb  305f148  (Only the first 10 of 29333 ports in this commit are shown above. View all ports for this commit)
Remove # $FreeBSD$ from Makefiles.
Wed, 19 Jun 2019
[ 10:16 danfe search for other commits by this committer ] Original commit   Revision:504533
- Fix the checks to avoid using `sys/dir.h' and thus undeprecate
- Define LICENSE (GPLv2) and install supplied documentation files
Wed, 12 Jun 2019
[ 06:52 bapt search for other commits by this committer ] Original commit   Revision:504003
Mark as deprecated a bunch of abandonware using sys/dir.h

sys/dir.h is going to be phased out soon, so mark as deprecated non maintained
abandonware using it.

PR:		21519
Mon, 9 Jun 2014
[ 11:21 olgeni search for other commits by this committer ] Original commit   Revision:357139 (Only the first 10 of 120 ports in this commit are shown above. View all ports for this commit)
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.

CR:		D196
Approved by:	portmgr (bapt)
Sun, 1 Jun 2014
[ 14:48 ohauer search for other commits by this committer ] Original commit   Revision:356131
- USE_(BZIP2|XZ) -> USES=tar:(bzip2|xz)
Thu, 27 Feb 2014
[ 13:43 ehaupt search for other commits by this committer ] Original commit   Revision:346330
Support staging
Fri, 20 Sep 2013
[ 15:58 bapt search for other commits by this committer ] Original commit   Revision:327711 (Only the first 10 of 103 ports in this commit are shown above. View all ports for this commit)
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
Thu, 16 Jun 2011
[ 10:41 bapt search for other commits by this committer ] Original commit 
Point to the new home
Make it fetchable again
Mon, 27 Oct 2008
[ 15:59 tabthorpe search for other commits by this committer ] Original commit 
- Reassign to ports
Thu, 23 Aug 2007
[ 04:00 tabthorpe search for other commits by this committer ] Original commit  (Only the first 10 of 58 ports in this commit are shown above. View all ports for this commit)
- change maintainer address on ports I maintain

Approved by:    clsung (mentor)
Sat, 21 Jul 2007
[ 01:21 ijliao search for other commits by this committer ] Original commit 
'actually' pass maintainership
[ 01:20 ijliao search for other commits by this committer ] Original commit 
upgrade to 2.12.a
pass maintainership to submitter

PR:             114768
Submitted by:   Thomas Abthorpe <thomas@goodking.ca>
Thu, 3 Aug 2006
[ 03:26 clsung search for other commits by this committer ] Original commit 
- maintainer is a committer
Fri, 20 Jan 2006
[ 14:18 arved search for other commits by this committer ] Original commit 
Fix build on sparc
Thu, 19 Jan 2006
[ 23:31 kris search for other commits by this committer ] Original commit 
BROKEN on sparc64: Does not compile
Wed, 4 Jan 2006
[ 05:56 edwin search for other commits by this committer ] Original commit 
Fix maintainership (set to submitter)
Thu, 29 Dec 2005
[ 03:48 edwin search for other commits by this committer ] Original commit 
[NEW PORT] cad/gplcver: A Verilog HDL simulator

        GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
        It also implements some of the 2001 P1364 standard features
        including all three PLI interfaces (tf_, acc_ and vpi_) as
        defined in the 2001 Language Reference Manual (LRM).

        Verilog is the name for both a language for describing
        electronic hardware called a hardware description language
        (HDL) and the name of the program that simulates HDL circuit
        descriptions to verify that described circuits will function
        correctly when the are constructed. Verilog is used only
        for describing digital logic circuits. Other HDLs such as
        Spice are used for describing analog circuits. There is an
        IEEE standard named P1364 that standardizes the Verilog HDL
        and the behavior of Verilog simulators.  Verilog is officially
        defined in the IEEE P1364 Language Reference Manual (LRM)
        that can be purchased from IEEE. There are many good books
        for learning that teach the Verilog HDL and/or that teach
        digital circuit design using Verilog.

        WWW: http://www.pragmatic-c.com/gpl-cver/

PR:             ports/80968
Submitted by:   Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>

Number of commits found: 17