21:58 Stefan Eßer (se) 

Remove WWW entries moved into port Makefiles

Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.

This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.

Approved by:		portmgr (tcberner)

    fb16dfe

20:33 sunpoet 

Update WWW: SF redirects to https://sourceforge.net/projects/<PROJECT_NAME>/

 

10:41 bapt 

Point to the new home
Make it fetchable again

03:48 edwin 

[NEW PORT] cad/gplcver: A Verilog HDL simulator

        GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
        It also implements some of the 2001 P1364 standard features
        including all three PLI interfaces (tf_, acc_ and vpi_) as
        defined in the 2001 Language Reference Manual (LRM).

        Verilog is the name for both a language for describing
        electronic hardware called a hardware description language
        (HDL) and the name of the program that simulates HDL circuit
        descriptions to verify that described circuits will function
        correctly when the are constructed. Verilog is used only
        for describing digital logic circuits. Other HDLs such as
        Spice are used for describing analog circuits. There is an
        IEEE standard named P1364 that standardizes the Verilog HDL
        and the behavior of Verilog simulators.  Verilog is officially
        defined in the IEEE P1364 Language Reference Manual (LRM)
        that can be purchased from IEEE. There are many good books
        for learning that teach the Verilog HDL and/or that teach
        digital circuit design using Verilog.

        WWW: http://www.pragmatic-c.com/gpl-cver/

PR:             ports/80968
Submitted by:   Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>