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Port details on branch 2022Q3
iverilog Verilog simulation and synthesis tool
12.0_1 cad on this many watch lists=4 search for ports that depend on this port Find issues related to this port Report an issue related to this port View this port on Repology. pkg-fallout 12.0Version of this port present on the latest quarterly branch.
Maintainer: kbowling@FreeBSD.org search for ports maintained by this maintainer
Port Added: 2001-02-13 08:02:19
Last Update: 2024-03-02 23:32:29
Commit Hash: 6302f27
People watching this port, also watch:: zip, unzip, cdrtools, autoconf, rsync
License: GPLv2
WWW:
https://steveicarus.github.io/iverilog/
Description:
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.
Homepage    cgit ¦ Codeberg ¦ GitHub ¦ GitLab ¦ SVNWeb

Manual pages:
FreshPorts has no man page information for this port.
pkg-plist: as obtained via: make generate-plist
Expand this list (57 items)
Collapse this list.
  1. /usr/local/share/licenses/iverilog-12.0_1/catalog.mk
  2. /usr/local/share/licenses/iverilog-12.0_1/LICENSE
  3. /usr/local/share/licenses/iverilog-12.0_1/GPLv2
  4. bin/iverilog
  5. bin/iverilog-vpi
  6. bin/vvp
  7. include/iverilog/_pli_types.h
  8. include/iverilog/acc_user.h
  9. include/iverilog/ivl_target.h
  10. include/iverilog/sv_vpi_user.h
  11. include/iverilog/veriuser.h
  12. include/iverilog/vpi_user.h
  13. lib/ivl/blif-s.conf
  14. lib/ivl/blif.conf
  15. lib/ivl/blif.tgt
  16. lib/ivl/cadpli.vpl
  17. lib/ivl/include/constants.vams
  18. lib/ivl/include/disciplines.vams
  19. lib/ivl/ivl
  20. lib/ivl/ivlpp
  21. lib/ivl/null-s.conf
  22. lib/ivl/null.conf
  23. lib/ivl/null.tgt
  24. lib/ivl/pcb-s.conf
  25. lib/ivl/pcb.conf
  26. lib/ivl/pcb.tgt
  27. lib/ivl/sizer-s.conf
  28. lib/ivl/sizer.conf
  29. lib/ivl/sizer.tgt
  30. lib/ivl/stub-s.conf
  31. lib/ivl/stub.conf
  32. lib/ivl/stub.tgt
  33. lib/ivl/system.vpi
  34. lib/ivl/vlog95-s.conf
  35. lib/ivl/vlog95.conf
  36. lib/ivl/vlog95.tgt
  37. lib/ivl/vpi_debug.vpi
  38. lib/ivl/v2005_math.vpi
  39. lib/ivl/v2009.vpi
  40. lib/ivl/va_math.vpi
  41. lib/ivl/vhdl-s.conf
  42. lib/ivl/vhdl_sys.vpi
  43. lib/ivl/vhdl_textio.vpi
  44. lib/ivl/vhdl.conf
  45. lib/ivl/vhdl.tgt
  46. lib/ivl/vhdlpp
  47. lib/ivl/vvp-s.conf
  48. lib/ivl/vvp.conf
  49. lib/ivl/vvp.tgt
  50. lib/libveriuser.a
  51. lib/libvpi.a
  52. share/man/man1/iverilog.1.gz
  53. share/man/man1/iverilog-vpi.1.gz
  54. share/man/man1/vvp.1.gz
  55. @owner
  56. @group
  57. @mode
Collapse this list.
Dependency lines:
  • iverilog>0:cad/iverilog
To install the port:
cd /usr/ports/cad/iverilog/ && make install clean
To add the package, run one of these commands:
  • pkg install cad/iverilog
  • pkg install iverilog
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.
PKGNAME: iverilog
Flavors: there is no flavor information for this port.
distinfo:
TIMESTAMP = 1681749176 SHA256 (steveicarus-iverilog-v12_0_GH0.tar.gz) = a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d SIZE (steveicarus-iverilog-v12_0_GH0.tar.gz) = 2995096

Packages (timestamps in pop-ups are UTC):
iverilog
ABIaarch64amd64armv6armv7i386powerpcpowerpc64powerpc64le
FreeBSD:13:latest12.0_112.0_111.012.0_112.0_1-11.0-
FreeBSD:13:quarterly12.012.0-12.012.012.012.012.0
FreeBSD:14:latest12.0_112.0_1-12.0_112.0_112.0-12.0
FreeBSD:14:quarterly12.012.0-12.012.012.012.012.0
FreeBSD:15:latest12.0_112.0_1n/a12.0n/a12.012.012.0
FreeBSD:15:quarterly--n/a-n/a---
Dependencies
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
Build dependencies:
  1. autoconf : devel/autoconf
  2. gperf : devel/gperf
  3. bison : devel/bison
  4. gmake>=4.3 : devel/gmake
Library dependencies:
  1. libreadline.so.8 : devel/readline
This port is required by:
for Run
  1. cad/py-cocotb
  2. java/veditor

Configuration Options:
No options to configure
Options name:
cad_iverilog
USES:
bison compiler:c++11-lang gmake readline
FreshPorts was unable to extract/find any pkg message
Master Sites:
Expand this list (1 items)
Collapse this list.
  1. https://codeload.github.com/steveicarus/iverilog/tar.gz/v12_0?dummy=/
Collapse this list.

There are no commits on branch 2022Q3 for this port