10:33 Hiroki Tagato (tagattie)  Author: Gian-Simon Purkert

cad/p5-Verilog-Perl: update to 3.478

Changelog: https://metacpan.org/dist/Verilog-Perl/changes

PR:		259336
Approved by:	otacilio.neto@bsd.com.br (maintainer timeout, >2 months)

    3787726

19:34 pi 

cad/p5-Verilog-Perl: 3.404 -> 3.418

Changes:
  http://cpansearch.perl.org/src/WSNYDER/Verilog-Perl-3.418/Changes
  Removed dependency of gcc. Now, p5-Verilog-Perl compiles with clang.

PR:		207050
Submitted by:	otacilio.neto@ee.ufcg.edu.br (maintainer)

 

18:59 garga 

- Update to 3.404
- Fix build, it needs gcc

PR:		191368
Submitted by:	otaciliodearaujo@gmail.com (maintainer)

 

21:42 rakuco 

Update to 3.400.

PR:		ports/177726
Submitted by:	Otacilio <otacilio.neto@ee.ufcg.edu.br> (maintainer)

 

21:49 swills 

- Update to 3.316

PR:		ports/171063
Approved by:	otacilio.neto@ee.ufcg.edu.br (maintainer)

12:54 miwi 

- Get Rid MD5 support

14:33 sylvio 

- Update to 3.251

PR:             ports/148726
Submitted by:   Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)

00:57 pgollucci 

- Update to 3.223

PR:             ports/142626
Submitted by:   myself (pgollucci@)
Approved by:    otacilio.neto@ee.ufcg.edu.br (maintainer)

02:02 pgollucci 

- Update to 3.222

PR:             ports/141552
Approved by:    maintainer
Submitted by:   myself (pgollucci@)

15:43 miwi 

- Update to 3.221

PR:             140231
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)

06:01 az 

Update to 2.213

PR:     ports/138081
Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)

00:42 pgollucci 

- Update to 2.11

PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)

11:01 garga 

The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>