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non port: cad/p5-Verilog-Perl/pkg-descr

Number of commits found: 5

Wednesday, 7 Sep 2022
21:58 Stefan Eßer (se) search for other commits by this committer
Remove WWW entries moved into port Makefiles

Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.

This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.

Approved by:		portmgr (tcberner)
commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 commit hash: fb16dfecae4a6efac9f3a78e0b759fb7a3c53de4 fb16dfe
Sunday, 16 Feb 2020
09:31 amdmi3 search for other commits by this committer
- Fix LICENSE
- Add LICENSE_FILE
- Silence stripping
- Update WWW

Approved by:	portmgr blanket
Original commitRevision:526258 
Thursday, 19 May 2016
10:21 amdmi3 search for other commits by this committer
- Fix trailing whitespace in pkg-descrs, categories [a-f]*

Approved by:	portmgr blanket
Original commitRevision:415498 
Friday, 27 Jun 2014
18:59 garga search for other commits by this committer
- Update to 3.404
- Fix build, it needs gcc

PR:		191368
Submitted by:	otaciliodearaujo@gmail.com (maintainer)
Original commitRevision:359597 
Tuesday, 26 May 2009
11:01 garga search for other commits by this committer
The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>
Original commit

Number of commits found: 5