p5-Verilog-Perl 3.251 cad =0

Building point for Verilog support in the Perl language
Maintained by: otacilio.neto@ee.ufcg.edu.br
Port Added: 26 May 2009 11:01:59
Also Listed In: perl5
License: not specified in port

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The Verilog-Perl library is a building point for Verilog support in the Perl 
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows 
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading 
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across 
  multiple files. Vrename uses a simple and efficient three step process. 
  First, you run vrename to create a list of signals in the design. You then 
  edit this list, changing as many symbols as you wish. Vrename is then run a 
  second time to apply the changes.

WWW:	http://www.veripool.org/wiki/verilog-perl

CVSWeb : Sources : Main Web Site : Distfiles Availability : PortsMon

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NOTE: FreshPorts displays only required dependencies information. Optional dependencies are not covered.
Required To Build: textproc/flex, devel/gmake, devel/bison, lang/perl5.8
Required To Run: lang/perl5.8
There are no ports dependent upon this port

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To install the port: cd /usr/ports/cad/p5-Verilog-Perl/ && make install clean
To add the package: pkg_add -r p5-Verilog-Perl

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Configuration Options

     No options to configure

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Master Sites:

ftp://ftp.cpan.org/pub/CPAN/modules/by-module/Verilog/

http://www.cpan.dk/modules/by-module/Verilog/

ftp://ftp.kddlabs.co.jp/lang/perl/CPAN/modules/by-module/Verilog/

http://ftp.jaist.ac.jp/pub/CPAN/modules/by-module/Verilog/

ftp://ftp.dti.ad.jp/pub/lang/CPAN/modules/by-module/Verilog/

ftp://ftp.sunet.se/pub/lang/perl/CPAN/modules/by-module/Verilog/

http://ring.nict.go.jp/archives/CPAN/modules/by-module/Verilog/

ftp://mirror.hiwaay.net/CPAN/modules/by-module/Verilog/

ftp://ftp.mirrorservice.org/sites/ftp.funet.fi/pub/languages/perl/CPAN/modules/by-module/Verilog/

http://at.cpan.org/modules/by-module/Verilog/

http://ring.riken.jp/archives/CPAN/modules/by-module/Verilog/

ftp://ftp.auckland.ac.nz/pub/perl/CPAN/modules/by-module/Verilog/

http://backpan.perl.org/modules/by-module/Verilog/

ftp://ftp.funet.fi/pub/languages/perl/CPAN/modules/by-module/Verilog/

http://cpan.nctu.edu.tw/modules/by-module/Verilog/

ftp://ftp.FreeBSD.org/pub/FreeBSD/ports/distfiles/

- Get Rid MD5 support

- Update to 3.251

PR:             ports/148726
Submitted by:   Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)

- Update to 3.223

PR:             ports/142626
Submitted by:   myself (pgollucci@)
Approved by:    otacilio.neto@ee.ufcg.edu.br (maintainer)

- Update to 3.222

PR:             ports/141552
Approved by:    maintainer
Submitted by:   myself (pgollucci@)

- Update to 3.221

PR:             140231
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
(maintainer)

- Fix compile problem with over optimization caused by -O2 flag for gcc in base
 prior OSVERSION 700042
- Unbreak

Approved by:    portmgr (miwi)
Feature safe:   yes

- mark BROKEN does not compile

Update to 2.213

PR:     ports/138081
Submitted by:   tacilio.net at ee.ufcg.edu.br (maintainer)

- Update to 2.11

PR:             ports/136485
Submitted by:   otacilio.neto@ee.ufcg.edu.br (maintainer)

- Add missing dependency (bison)

Reported by:    QAT
Pointyhat to:   garga

The Verilog-Perl library is a building point for Verilog support in the Perl
language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
  easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
  post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
  cross references and makes it easy to rename signal and module names across
  multiple files. Vrename uses a simple and efficient three step process.
  First, you run vrename to create a list of signals in the design. You then
  edit this list, changing as many symbols as you wish. Vrename is then run a
  second time to apply the changes.

WWW:    http://www.veripool.org/wiki/verilog-perl

PR:             ports/134124
Submitted by:   Otacílio de Araújo Ramos Neto <otacilio.neto at
ee.ufcg.edu.br>

12 vulnerabilities affecting 17 ports have been reported in the past 14 days

^* - modified, not new

All vulnerabilities