Ports marked with a ^* actually reside within another category but have cad listed as a secondary category.

hs-verismith Verilog fuzzer

1.1.0_1 1.1.0_1Version of this port present on the latest quarterly branch.

Maintainer: yuri@FreeBSD.org

Port Added: 2025-07-22 10:27:05

Also Listed In: haskell

License: GPLv3

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• hs-verismith>0:cad/hs-verismith

ngspice_rework Mixed-signal circuit simulator derived from Spice and Cider

44.2 44.2Version of this port present on the latest quarterly branch.

Maintainer: kevinz5000@gmail.com

Port Added: 2025-09-02 21:15:05

License: BSD3CLAUSE BSD4CLAUSE LGPL21+

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• ngspice_rework>0:cad/ngspice_rework

openvsp Create a 3D model of an aircraft defined by engineering parameters

3.43.1 3.43.1Version of this port present on the latest quarterly branch.

Maintainer: fernape@FreeBSD.org

Port Added: 2025-07-04 18:03:10

License: NOSA13

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• openvsp>0:cad/openvsp

scilab Scientific software package for numerical computations

6.1.1_23^* Package not present on quarterly.This port was created during this quarter. It will be in the next quarterly branch but not the current one.

There is no maintainer for this port.

Any concerns regarding this port should be directed to the FreeBSD Ports mailing list via ports@FreeBSD.org

Port Added: 2025-07-14 13:30:23

Also Listed In: java math

License: GPLv2 BSD3CLAUSE

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• scilab>0:math/scilab