GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
implements some of the 2001 P1364 standard features including all three
PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
Reference Manual (LRM).
Verilog is the name for both a language for describing electronic hardware
called a hardware description language (HDL) and the name of the program
that simulates HDL circuit descriptions to verify that described circuits
will function correctly when the are constructed. Verilog is used only for
describing digital logic circuits. Other HDLs such as Spice are used for
describing analog circuits. There is an IEEE standard named P1364 that
standardizes the Verilog HDL and the behavior of Verilog simulators.
Verilog is officially defined in the IEEE P1364 Language Reference
Manual (LRM) that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach digital circuit
design using Verilog.
===> The following configuration options are available for gplcver-2.12.a:
DOCS=on: Build and/or install documentation
===> Use 'make config' to modify these settings
cad/gplcver: fix build on recent FreeBSD
The option -export-dynamic is a linker option not (no longer?)
understood by the compiler; pass -rdynamic to the compiler to have it
pass -export-dynamic to the linker instead.
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner)
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above )
Mark as deprecated a bunch of abandonware using sys/dir.h
sys/dir.h is going to be phased out soon, so mark as deprecated non maintained
abandonware using it.
PR: 21519
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.
CR: D196
Approved by: portmgr (bapt)
[NEW PORT] cad/gplcver: A Verilog HDL simulator
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
