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Port details
gplcver Verilog HDL simulator
2.12.a cad on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port
2.12.aVersion of this port present on the latest quarterly branch.
Deprecated DEPRECATED: Abandonware using sys/dir.h
Expiration Date EXPIRATION DATE: 2019-07-12

There is no maintainer for this port.
Any concerns regarding this port should be directed to the FreeBSD Ports mailing list via ports@FreeBSD.org search for ports maintained by this maintainer
Port Added: 2005-12-29 03:53:04
Last Update: 2019-06-12 07:52:51
SVN Revision: 504003
License: not specified in port
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also
implements some of the 2001 P1364 standard features including all three
PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language
Reference Manual (LRM).

Verilog is the name for both a language for describing electronic hardware
called a hardware description language (HDL) and the name of the program
that simulates HDL circuit descriptions to verify that described circuits
will function correctly when the are constructed. Verilog is used only for
describing digital logic circuits. Other HDLs such as Spice are used for
describing analog circuits. There is an IEEE standard named P1364 that
standardizes the Verilog HDL and the behavior of Verilog simulators.
Verilog is officially defined in the IEEE P1364 Language Reference
Manual (LRM) that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach digital circuit
design using Verilog.

WWW: https://sourceforge.net/projects/gplcver/
SVNWeb : Homepage
    Pseudo-pkg-plist information, but much better, from make generate-plist
    Expand this list (1 items)
  1. bin/cver
  2. Collapse this list.
Dependency lines:
  • gplcver>0:cad/gplcver

To install the port: cd /usr/ports/cad/gplcver/ && make install clean
To add the package: pkg install gplcver

PKGNAME: gplcver

There is no flavor information for this port.

distinfo:

SHA256 (gplcver-2.12a.src.tar.bz2) = f7d94677677f10c2d1e366eda2d01a652ef5f30d167660905c100f52f1a46e75
SIZE (gplcver-2.12a.src.tar.bz2) = 1224470


NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.

Build dependencies:
  1. gmake : devel/gmake
There are no ports dependent upon this port

Configuration Options
     No options to configure

USES:
tar:bzip2 gmake

Master Sites:
  1. http://cytranet.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  2. http://downloads.sourceforge.net/project/gplcver/gplcver/2.12a/
  3. http://excellmedia.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  4. http://freefr.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  5. http://jaist.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  6. http://kent.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  7. http://nchc.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  8. http://netcologne.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  9. http://netix.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  10. http://superb-dca2.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  11. http://superb-sea2.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  12. http://ufpr.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  13. http://vorboss.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  14. https://cytranet.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  15. https://downloads.sourceforge.net/project/gplcver/gplcver/2.12a/
  16. https://excellmedia.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  17. https://freefr.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  18. https://jaist.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  19. https://kent.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  20. https://nchc.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  21. https://netcologne.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  22. https://netix.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  23. https://superb-dca2.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  24. https://superb-sea2.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  25. https://ufpr.dl.sourceforge.net/project/gplcver/gplcver/2.12a/
  26. https://vorboss.dl.sourceforge.net/project/gplcver/gplcver/2.12a/

Number of commits found: 17

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
12 Jun 2019 06:52:51
Original commit files touched by this commit  2.12.a
Revision:504003
bapt search for other commits by this committer
Mark as deprecated a bunch of abandonware using sys/dir.h

sys/dir.h is going to be phased out soon, so mark as deprecated non maintained
abandonware using it.

PR:		21519
20 Jan 2017 20:33:31
Original commit files touched by this commit  2.12.a
Revision:431996
sunpoet search for other commits by this committer
Update WWW: SF redirects to https://sourceforge.net/projects/<PROJECT_NAME>/
09 Jun 2014 11:21:53
Original commit files touched by this commit  2.12.a
Revision:357139
olgeni search for other commits by this committer
Remove indefinite articles and trailing periods from COMMENT, plus
minor COMMENT typos and surrounding whitespace fixes. Categories A-C.

CR:		D196
Approved by:	portmgr (bapt)
01 Jun 2014 14:48:08
Original commit files touched by this commit  2.12.a
Revision:356131
ohauer search for other commits by this committer
- USE_(BZIP2|XZ) -> USES=tar:(bzip2|xz)
27 Feb 2014 13:43:28
Original commit files touched by this commit  2.12.a
Revision:346330
ehaupt search for other commits by this committer
Support staging
20 Sep 2013 15:58:42
Original commit files touched by this commit  2.12.a
Revision:327711
bapt search for other commits by this committer
Add NO_STAGE all over the place in preparation for the staging support (cat:
cad)
16 Jun 2011 10:41:31
Original commit files touched by this commit  2.12.a

bapt search for other commits by this committer
Point to the new home
Make it fetchable again
20 Mar 2011 12:54:45
Original commit files touched by this commit  2.12.a

miwi search for other commits by this committer
- Get Rid MD5 support
27 Oct 2008 15:59:27
Original commit files touched by this commit  2.12.a

tabthorpe search for other commits by this committer
- Reassign to ports
23 Aug 2007 04:00:04
Original commit files touched by this commit  2.12.a

tabthorpe search for other commits by this committer
- change maintainer address on ports I maintain

Approved by:    clsung (mentor)
21 Jul 2007 01:21:52
Original commit files touched by this commit  2.12.a

ijliao search for other commits by this committer
'actually' pass maintainership
21 Jul 2007 01:20:50
Original commit files touched by this commit  2.12.a

ijliao search for other commits by this committer
upgrade to 2.12.a
pass maintainership to submitter

PR:             114768
Submitted by:   Thomas Abthorpe <thomas@goodking.ca>
03 Aug 2006 03:26:38
Original commit files touched by this commit  2.11.a

clsung search for other commits by this committer
- maintainer is a committer
20 Jan 2006 14:18:34
Original commit files touched by this commit  2.11.a

arved search for other commits by this committer
Fix build on sparc
19 Jan 2006 23:31:12
Original commit files touched by this commit  2.11.a

kris search for other commits by this committer
BROKEN on sparc64: Does not compile
04 Jan 2006 05:56:54
Original commit files touched by this commit  2.11.a

edwin search for other commits by this committer
Fix maintainership (set to submitter)
29 Dec 2005 03:48:58
Original commit files touched by this commit  2.11.a

edwin search for other commits by this committer
[NEW PORT] cad/gplcver: A Verilog HDL simulator

        GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
        It also implements some of the 2001 P1364 standard features
        including all three PLI interfaces (tf_, acc_ and vpi_) as
        defined in the 2001 Language Reference Manual (LRM).

        Verilog is the name for both a language for describing
        electronic hardware called a hardware description language
        (HDL) and the name of the program that simulates HDL circuit
        descriptions to verify that described circuits will function
        correctly when the are constructed. Verilog is used only
        for describing digital logic circuits. Other HDLs such as
        Spice are used for describing analog circuits. There is an
        IEEE standard named P1364 that standardizes the Verilog HDL
        and the behavior of Verilog simulators.  Verilog is officially
        defined in the IEEE P1364 Language Reference Manual (LRM)
        that can be purchased from IEEE. There are many good books
        for learning that teach the Verilog HDL and/or that teach
        digital circuit design using Verilog.

        WWW: http://www.pragmatic-c.com/gpl-cver/

PR:             ports/80968
Submitted by:   Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>

Number of commits found: 17

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