23:32 Nuno Teixeira (eduardo) 

cad/iverilog: Move man pages to share/man

Approved by:	portmgr (blanket)

    6302f27

19:21 zeising 

cad/iverilog: Update to 11.0

Update cad/iverilog to 11.0.  The first release in the 11 branch.

 

12:17 zeising 

Update to 10.0

Committed from:	EuroBSDCon 2015

 

07:19 bapt 

Cleanup plist

 

16:08 zeising 

Update to 0.9.7.

Stagify.

 

12:58 stas 

- Update to 0.9.1.

22:04 stas 

- Update to 0.8.7.

13:34 stas 

- Update to 0.8.2
- Fix compiling with gcc 4.1
- Change my email

Approved by:    sem (mentor)

13:16 arved 

Update to 0.8

PR:             72949
Submitted by:   Joachim Strombergson <watchman@ludd.ltu.se>

16:02 linimon 

Update to 20031202 snapshot.  Summary of changes listed on
ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20031202.txt:

Combination 64bit/32bit runtime support now works fully on AMD64
systems; wait on lists of named events now works; there is no
longer a common iverilog.conf, instead there are target specific
foo.conf files with a new and cleaner format; 64bit values are more
portably handled; several synthesis bugs related to the control inputs
of flip-flops have been fixed.

Committer is marking this BROKEN on 4.x while we investigate install
problems.  It works on 5.x only for now.

PR:             ports/60162
Submitted by:   Joachim Strombergson <watchman@ludd.luth.se> (maintainer)

10:02 linimon 

Maintainer Update to latest snapshot.  Changes: add AMD64 support
(experimental); time 0 race resolution; identation cleanup; manpage
update.
PR: ports/58320

18:18 will 

Fix this port and remove BROKEN.

17:49 keichii 

Update to iverilog 0.7

Submitted by:    Joachim Str?mbergson <watchman@ludd.luth.se>

03:04 kris 

Add missing files

11:02 ijliao 

add iverilog, a Verilog simulation and synthesis tool