| Port details |
- py-verilog-parser Lark-based parser for structural Verilog netlists
- 0.0.7 cad
 =0      Package not present on quarterly.This port was created during this quarter. It will be in the next quarterly branch but not the current one. - Maintainer: spaciouscoder78@disroot.org
- Port Added: 2025-10-30 18:09:08
- Last Update: 2025-10-30 18:06:51
- Commit Hash: 0c3b043
- Also Listed In: python
- License: AGPLv3+
- WWW:
- https://codeberg.org/tok/py-verilog-parser
- Description:
- Lark-based parser for Verilog netlists (structural Verilog without behavioral
statements). This is meant to be used to read netlists as generated by HDL logic
synthesizers such as Yosys.
  ¦  ¦  ¦  ¦ 
- Manual pages:
- FreshPorts has no man page information for this port.
- pkg-plist: as obtained via:
make generate-plist - There is no configure plist information for this port.
- USE_RC_SUBR (Service Scripts)
- no SUBR information found for this port
- Dependency lines:
-
- ${PYTHON_PKGNAMEPREFIX}verilog_parser>0:cad/py-verilog-parser@${PY_FLAVOR}
- To install the port:
- cd /usr/ports/cad/py-verilog-parser/ && make install clean
- To add the package, run one of these commands:
- pkg install cad/py-verilog-parser
- pkg install py311-verilog_parser
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.
NOTE: This is a Python port. Instead of py311-verilog_parser listed in the above command, you can pick from the names under the Packages section.- PKGNAME: py311-verilog_parser
- Package flavors (<flavor>: <package>)
- py311: py311-verilog_parser
- distinfo:
- TIMESTAMP = 1760924808
SHA256 (verilog_parser-0.0.7.tar.gz) = dbe6db18bc74398fa481ca373205818065cac2ac0e165886ce373b01bdf8e0f7
SIZE (verilog_parser-0.0.7.tar.gz) = 7197
Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- py311-setuptools>0 : devel/py-setuptools@py311
- py311-lark>=1.2.2<2 : devel/py-lark@py311
- py311-wheel>=0.45.1 : devel/py-wheel@py311
- python3.11 : lang/python311
- py311-build>=0 : devel/py-build@py311
- py311-installer>=0 : devel/py-installer@py311
- Test dependencies:
-
- python3.11 : lang/python311
- Runtime dependencies:
-
- python3.11 : lang/python311
- There are no ports dependent upon this port
Configuration Options:- No options to configure
- Options name:
- cad_py-verilog-parser
- USES:
- python
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
|
Number of commits found: 1
| Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
| Commit | Credits | Log message |
|---|
0.0.7
30 Oct 2025 18:06:51
 |
Älven (alven)
Author: Aryan Karamtoth |
cad/py-verilog-parser: [NEW PORT] Lark-based parser for structural Verilog
netlists
PR: 290373
Approved by: yuri@ (Mentor) |
Number of commits found: 1
|
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