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Port details
yosys Yosys Open SYnthesis Suite
0.8.1116_1 devel on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port 0.8.1116Version of this port present on the latest quarterly branch.
Maintainer: jsorocil@gmail.com search for ports maintained by this maintainer
Port Added: 2018-06-06 14:20:08
Last Update: 2019-07-26 21:46:57
SVN Revision: 507372
License: ISCL
Description:
SVNWeb : Homepage
pkg-plist: as obtained via: make generate-plist
Expand this list (124 items)
  1. /usr/local/share/licenses/yosys-0.8.1116_1/catalog.mk
  2. /usr/local/share/licenses/yosys-0.8.1116_1/LICENSE
  3. /usr/local/share/licenses/yosys-0.8.1116_1/ISCL
  4. bin/yosys
  5. bin/yosys-config
  6. bin/yosys-filterlib
  7. bin/yosys-smtbmc
  8. share/yosys/achronix/speedster22i/cells_map.v
  9. share/yosys/achronix/speedster22i/cells_sim.v
  10. share/yosys/adff2dff.v
  11. share/yosys/anlogic/arith_map.v
  12. share/yosys/anlogic/cells_map.v
  13. share/yosys/anlogic/cells_sim.v
  14. share/yosys/anlogic/dram_init_16x4.vh
  15. share/yosys/anlogic/drams.txt
  16. share/yosys/anlogic/drams_map.v
  17. share/yosys/anlogic/eagle_bb.v
  18. share/yosys/cells.lib
  19. share/yosys/cmp2lut.v
  20. share/yosys/coolrunner2/cells_latch.v
  21. share/yosys/coolrunner2/cells_sim.v
  22. share/yosys/coolrunner2/tff_extract.v
  23. share/yosys/coolrunner2/xc2_dff.lib
  24. share/yosys/dff2ff.v
  25. share/yosys/ecp5/arith_map.v
  26. share/yosys/ecp5/bram.txt
  27. share/yosys/ecp5/bram_conn_1.vh
  28. share/yosys/ecp5/bram_conn_18.vh
  29. share/yosys/ecp5/bram_conn_2.vh
  30. share/yosys/ecp5/bram_conn_4.vh
  31. share/yosys/ecp5/bram_conn_9.vh
  32. share/yosys/ecp5/bram_init_1_2_4.vh
  33. share/yosys/ecp5/bram_init_9_18_36.vh
  34. share/yosys/ecp5/brams_map.v
  35. share/yosys/ecp5/cells_bb.v
  36. share/yosys/ecp5/cells_map.v
  37. share/yosys/ecp5/cells_sim.v
  38. share/yosys/ecp5/dram.txt
  39. share/yosys/ecp5/drams_map.v
  40. share/yosys/ecp5/latches_map.v
  41. share/yosys/gate2lut.v
  42. share/yosys/gowin/arith_map.v
  43. share/yosys/gowin/bram.txt
  44. share/yosys/gowin/brams_init3.vh
  45. share/yosys/gowin/brams_map.v
  46. share/yosys/gowin/cells_map.v
  47. share/yosys/gowin/cells_sim.v
  48. share/yosys/gowin/dram.txt
  49. share/yosys/gowin/drams_map.v
  50. share/yosys/greenpak4/cells_blackbox.v
  51. share/yosys/greenpak4/cells_latch.v
  52. share/yosys/greenpak4/cells_map.v
  53. share/yosys/greenpak4/cells_sim.v
  54. share/yosys/greenpak4/cells_sim_ams.v
  55. share/yosys/greenpak4/cells_sim_digital.v
  56. share/yosys/greenpak4/cells_sim_wip.v
  57. share/yosys/greenpak4/gp_dff.lib
  58. share/yosys/ice40/arith_map.v
  59. share/yosys/ice40/brams.txt
  60. share/yosys/ice40/brams_init1.vh
  61. share/yosys/ice40/brams_init2.vh
  62. share/yosys/ice40/brams_init3.vh
  63. share/yosys/ice40/brams_map.v
  64. share/yosys/ice40/cells_map.v
  65. share/yosys/ice40/cells_sim.v
  66. share/yosys/ice40/latches_map.v
  67. share/yosys/include/backends/ilang/ilang_backend.h
  68. share/yosys/include/frontends/ast/ast.h
  69. share/yosys/include/kernel/celledges.h
  70. share/yosys/include/kernel/celltypes.h
  71. share/yosys/include/kernel/consteval.h
  72. share/yosys/include/kernel/hashlib.h
  73. share/yosys/include/kernel/log.h
  74. share/yosys/include/kernel/macc.h
  75. share/yosys/include/kernel/modtools.h
  76. share/yosys/include/kernel/register.h
  77. share/yosys/include/kernel/rtlil.h
  78. share/yosys/include/kernel/satgen.h
  79. share/yosys/include/kernel/sigtools.h
  80. share/yosys/include/kernel/utils.h
  81. share/yosys/include/kernel/yosys.h
  82. share/yosys/include/libs/ezsat/ezminisat.h
  83. share/yosys/include/libs/ezsat/ezsat.h
  84. share/yosys/include/libs/sha1/sha1.h
  85. share/yosys/include/passes/fsm/fsmdata.h
  86. share/yosys/intel/a10gx/cells_map.v
  87. share/yosys/intel/a10gx/cells_sim.v
  88. share/yosys/intel/common/altpll_bb.v
  89. share/yosys/intel/common/brams.txt
  90. share/yosys/intel/common/brams_map.v
  91. share/yosys/intel/common/m9k_bb.v
  92. share/yosys/intel/cyclone10/cells_map.v
  93. share/yosys/intel/cyclone10/cells_sim.v
  94. share/yosys/intel/cycloneiv/cells_map.v
  95. share/yosys/intel/cycloneiv/cells_sim.v
  96. share/yosys/intel/cycloneive/cells_map.v
  97. share/yosys/intel/cycloneive/cells_sim.v
  98. share/yosys/intel/cyclonev/cells_map.v
  99. share/yosys/intel/cyclonev/cells_sim.v
  100. share/yosys/intel/max10/cells_map.v
  101. share/yosys/intel/max10/cells_sim.v
  102. share/yosys/pmux2mux.v
  103. share/yosys/python3/smtio.py
  104. share/yosys/sf2/arith_map.v
  105. share/yosys/sf2/cells_map.v
  106. share/yosys/sf2/cells_sim.v
  107. share/yosys/simcells.v
  108. share/yosys/simlib.v
  109. share/yosys/techmap.v
  110. share/yosys/xilinx/arith_map.v
  111. share/yosys/xilinx/brams.txt
  112. share/yosys/xilinx/brams_bb.v
  113. share/yosys/xilinx/brams_init_16.vh
  114. share/yosys/xilinx/brams_init_18.vh
  115. share/yosys/xilinx/brams_init_32.vh
  116. share/yosys/xilinx/brams_init_36.vh
  117. share/yosys/xilinx/brams_map.v
  118. share/yosys/xilinx/cells_map.v
  119. share/yosys/xilinx/cells_sim.v
  120. share/yosys/xilinx/cells_xtra.v
  121. share/yosys/xilinx/drams.txt
  122. share/yosys/xilinx/drams_map.v
  123. share/yosys/xilinx/ff_map.v
  124. share/yosys/xilinx/lut_map.v
Collapse this list.
Dependency lines:
  • yosys>0:devel/yosys
To install the port: cd /usr/ports/devel/yosys/ && make install clean
To add the package: pkg install yosys
PKGNAME: yosys
Flavors: there is no flavor information for this port.
distinfo:

Dependencies
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
Build dependencies:
  1. abc : cad/abc
  2. bash : shells/bash
  3. gawk : lang/gawk
  4. bison : devel/bison
  5. gmake : devel/gmake
  6. pkgconf>=1.3.0_1 : devel/pkgconf
  7. python3.6 : lang/python36
Runtime dependencies:
  1. python3.6 : lang/python36
Library dependencies:
  1. libffi.so : devel/libffi
  2. libreadline.so.8 : devel/readline
  3. libtcl86.so : lang/tcl86
This port is required by:
for Build
  1. devel/lattice-ice40-examples-hx1k
  2. devel/lattice-ice40-examples-hx8k
for Run
  1. devel/lattice-ice40-tools

Configuration Options

USES:

Master Sites:
  1. https://codeload.github.com/YosysHQ/yosys/tar.gz/yosys-0.8-1116-g90ec2cda?dummy=/

Number of commits found: 11

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
26 Jul 2019 20:46:57
Original commit files touched by this commit  0.8.1116_1
Revision:507372
gerald search for other commits by this committer
Bump PORTREVISION for ports depending on the canonical version of GCC
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.

This includes ports
 - with USE_GCC=yes or USE_GCC=any,
 - with USES=fortran,
 - using Mk/bsd.octave.mk which in turn features USES=fortran, and
 - with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
   c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.

PR:		238330
28 Jun 2019 04:24:05
Original commit files touched by this commit  0.8.1116
Revision:505260
tobik search for other commits by this committer
devel/yosys: Fix version going backwards after r505157

Follow the Porter's Handbook [1] to get a version > 0.8 to avoid
bumping PORTEPOCH.

[1]
https://www.freebsd.org/doc/en/books/porters-handbook/makefile-distfiles.html#makefile-master_sites-github-ex5

PR:		238484
Pointy hat:	manu
26 Jun 2019 14:22:44
Original commit files touched by this commit  g20190531
Revision:505157
manu search for other commits by this committer
yosys: Update to latest git master

Use the last git master so we can use nextpnr and project trellis for
ECP5 FPGAs.

PR:		238484
Approved by:	maintainer timeout (jsorocil@gmail.com, 2 weeks)
09 Apr 2019 14:04:50
Original commit files touched by this commit  0.8_2
Revision:498476
sunpoet search for other commits by this committer
Update devel/readline to 8.0

- Bump PORTREVISION of dependent ports for shlib change

Changes:	https://tiswww.case.edu/php/chet/readline/CHANGES
PR:		236156
Exp-run by:	antoine
12 Dec 2018 01:35:36
Original commit files touched by this commit  0.8_1
Revision:487272
gerald search for other commits by this committer
Bump PORTREVISION for ports depending on the canonical version of GCC
defined via Mk/bsd.default-versions.mk which has moved from GCC 7.4 t
GCC 8.2 under most circumstances.

This includes ports
 - with USE_GCC=yes or USE_GCC=any,
 - with USES=fortran,
 - using Mk/bsd.octave.mk which in turn features USES=fortran, and
 - with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
   c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, as a double check, everything INDEX-11 showed depending on lang/gcc7.

PR:		231590
08 Dec 2018 16:03:25
Original commit files touched by this commit  0.8
Revision:486958
antoine search for other commits by this committer
Fix plist
14 Nov 2018 14:43:18
Original commit files touched by this commit  0.8
Revision:484926
tobik search for other commits by this committer
devel/yosys: Update to 0.8

PR:		233077
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D17642
09 Nov 2018 19:18:35
Original commit files touched by this commit  0.7.783
Revision:484538
swills search for other commits by this committer
devel/yosys: use simpler way of dealing with compiler issues

PR:		232117
Submitted by:	jbeich
Pointyhat to:	swills
09 Nov 2018 17:31:57
Original commit files touched by this commit  0.7.783
Revision:484532
swills search for other commits by this committer
devel/yosys: fix build with GCC-based architectures

PR:		232650
Submitted by:	Piotr Kubaj <pkubaj@anongoth.pl>
Approved by:	maintainer timeout (jsorocil@gmail.com, >2 weeks)
18 Sep 2018 11:01:51
Original commit files touched by this commit  0.7.783
Revision:480010
linimon search for other commits by this committer
Mark these ports as broken on powerpc64.

While here, pet portlint.

Approved by:	portmgr (tier-2 blanket)
06 Jun 2018 14:19:51
Original commit files touched by this commit  0.7.783
Revision:471844
tobik search for other commits by this committer
New port: devel/yosys

Yosys is a framework for Verilog RTL synthesis.  It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

WWW: http://www.clifford.at/yosys/

PR:		227591
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D15632

Number of commits found: 11

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