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Port details
yosys Yosys Open SYnthesis Suite
0.8_2 devel on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port
Maintainer: jsorocil@gmail.com search for ports maintained by this maintainer
Port Added: 2018-06-06 14:20:08
Last Update: 2019-04-09 15:04:50
SVN Revision: 498476
License: ISCL
Yosys is a framework for Verilog RTL synthesis.  It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

WWW: http://www.clifford.at/yosys/
SVNWeb : Homepage
    Pseudo-pkg-plist information, but much better, from make generate-plist
    Expand this list (94 items)
  1. /usr/local/share/licenses/yosys-0.8_2/catalog.mk
  2. /usr/local/share/licenses/yosys-0.8_2/LICENSE
  3. /usr/local/share/licenses/yosys-0.8_2/ISCL
  4. bin/yosys
  5. bin/yosys-config
  6. bin/yosys-filterlib
  7. bin/yosys-smtbmc
  8. share/yosys/achronix/speedster22i/cells_map.v
  9. share/yosys/achronix/speedster22i/cells_sim.v
  10. share/yosys/adff2dff.v
  11. share/yosys/cells.lib
  12. share/yosys/coolrunner2/cells_latch.v
  13. share/yosys/coolrunner2/cells_sim.v
  14. share/yosys/coolrunner2/tff_extract.v
  15. share/yosys/coolrunner2/xc2_dff.lib
  16. share/yosys/dff2ff.v
  17. share/yosys/ecp5/arith_map.v
  18. share/yosys/ecp5/cells_map.v
  19. share/yosys/ecp5/cells_sim.v
  20. share/yosys/ecp5/dram.txt
  21. share/yosys/ecp5/drams_map.v
  22. share/yosys/gowin/cells_map.v
  23. share/yosys/gowin/cells_sim.v
  24. share/yosys/greenpak4/cells_blackbox.v
  25. share/yosys/greenpak4/cells_latch.v
  26. share/yosys/greenpak4/cells_map.v
  27. share/yosys/greenpak4/cells_sim.v
  28. share/yosys/greenpak4/cells_sim_ams.v
  29. share/yosys/greenpak4/cells_sim_digital.v
  30. share/yosys/greenpak4/cells_sim_wip.v
  31. share/yosys/greenpak4/gp_dff.lib
  32. share/yosys/ice40/arith_map.v
  33. share/yosys/ice40/brams.txt
  34. share/yosys/ice40/brams_init1.vh
  35. share/yosys/ice40/brams_init2.vh
  36. share/yosys/ice40/brams_init3.vh
  37. share/yosys/ice40/brams_map.v
  38. share/yosys/ice40/cells_map.v
  39. share/yosys/ice40/cells_sim.v
  40. share/yosys/ice40/latches_map.v
  41. share/yosys/include/backends/ilang/ilang_backend.h
  42. share/yosys/include/frontends/ast/ast.h
  43. share/yosys/include/kernel/celledges.h
  44. share/yosys/include/kernel/celltypes.h
  45. share/yosys/include/kernel/consteval.h
  46. share/yosys/include/kernel/hashlib.h
  47. share/yosys/include/kernel/log.h
  48. share/yosys/include/kernel/macc.h
  49. share/yosys/include/kernel/modtools.h
  50. share/yosys/include/kernel/register.h
  51. share/yosys/include/kernel/rtlil.h
  52. share/yosys/include/kernel/satgen.h
  53. share/yosys/include/kernel/sigtools.h
  54. share/yosys/include/kernel/utils.h
  55. share/yosys/include/kernel/yosys.h
  56. share/yosys/include/libs/ezsat/ezminisat.h
  57. share/yosys/include/libs/ezsat/ezsat.h
  58. share/yosys/include/libs/sha1/sha1.h
  59. share/yosys/include/passes/fsm/fsmdata.h
  60. share/yosys/intel/a10gx/cells_map.v
  61. share/yosys/intel/a10gx/cells_sim.v
  62. share/yosys/intel/common/altpll_bb.v
  63. share/yosys/intel/common/brams.txt
  64. share/yosys/intel/common/brams_map.v
  65. share/yosys/intel/common/m9k_bb.v
  66. share/yosys/intel/cyclone10/cells_map.v
  67. share/yosys/intel/cyclone10/cells_sim.v
  68. share/yosys/intel/cycloneiv/cells_map.v
  69. share/yosys/intel/cycloneiv/cells_sim.v
  70. share/yosys/intel/cycloneive/cells_map.v
  71. share/yosys/intel/cycloneive/cells_sim.v
  72. share/yosys/intel/cyclonev/cells_map.v
  73. share/yosys/intel/cyclonev/cells_sim.v
  74. share/yosys/intel/max10/cells_map.v
  75. share/yosys/intel/max10/cells_sim.v
  76. share/yosys/pmux2mux.v
  77. share/yosys/python3/smtio.py
  78. share/yosys/simcells.v
  79. share/yosys/simlib.v
  80. share/yosys/techmap.v
  81. share/yosys/xilinx/arith_map.v
  82. share/yosys/xilinx/brams.txt
  83. share/yosys/xilinx/brams_bb.v
  84. share/yosys/xilinx/brams_init_16.vh
  85. share/yosys/xilinx/brams_init_18.vh
  86. share/yosys/xilinx/brams_init_32.vh
  87. share/yosys/xilinx/brams_init_36.vh
  88. share/yosys/xilinx/brams_map.v
  89. share/yosys/xilinx/cells_map.v
  90. share/yosys/xilinx/cells_sim.v
  91. share/yosys/xilinx/cells_xtra.v
  92. share/yosys/xilinx/drams.txt
  93. share/yosys/xilinx/drams_map.v
  94. share/yosys/xilinx/lut2lut.v
  95. Collapse this list.
Dependency lines:
  • yosys>0:devel/yosys

To install the port: cd /usr/ports/devel/yosys/ && make install clean
To add the package: pkg install yosys

PKGNAME: yosys

There is no flavor information for this port.

distinfo:

TIMESTAMP = 1540309364
SHA256 (YosysHQ-yosys-yosys-0.8_GH0.tar.gz) = 07760fe732003585b26d97f9e02bcddf242ff7fc33dbd415446ac7c70e85c66f
SIZE (YosysHQ-yosys-yosys-0.8_GH0.tar.gz) = 1118433


NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.

Build dependencies:
  1. abc : cad/abc
  2. bash : shells/bash
  3. gawk : lang/gawk
  4. bison : devel/bison
  5. gmake : devel/gmake
  6. pkgconf>=1.3.0_1 : devel/pkgconf
  7. python3.6 : lang/python36
Runtime dependencies:
  1. python3.6 : lang/python36
Library dependencies:
  1. libffi.so : devel/libffi
  2. libreadline.so.8 : devel/readline
  3. libtcl86.so : lang/tcl86

This port is required by:

for Build for Run
Configuration Options
     No options to configure

USES:
bison compiler:c++11-lang gmake pkgconfig python:3.6+ readline  shebangfix tcl

Master Sites:
  1. https://codeload.github.com/YosysHQ/yosys/tar.gz/yosys-0.8?dummy=/

Number of commits found: 8

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
09 Apr 2019 14:04:50
Original commit files touched by this commit  0.8_2
Revision:498476
sunpoet search for other commits by this committer
Update devel/readline to 8.0

- Bump PORTREVISION of dependent ports for shlib change

Changes:	https://tiswww.case.edu/php/chet/readline/CHANGES
PR:		236156
Exp-run by:	antoine
12 Dec 2018 01:35:36
Original commit files touched by this commit  0.8_1
Revision:487272
gerald search for other commits by this committer
Bump PORTREVISION for ports depending on the canonical version of GCC
defined via Mk/bsd.default-versions.mk which has moved from GCC 7.4 t
GCC 8.2 under most circumstances.

This includes ports
 - with USE_GCC=yes or USE_GCC=any,
 - with USES=fortran,
 - using Mk/bsd.octave.mk which in turn features USES=fortran, and
 - with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
   c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, as a double check, everything INDEX-11 showed depending on lang/gcc7.

PR:		231590
08 Dec 2018 16:03:25
Original commit files touched by this commit  0.8
Revision:486958
antoine search for other commits by this committer
Fix plist
14 Nov 2018 14:43:18
Original commit files touched by this commit  0.8
Revision:484926
tobik search for other commits by this committer
devel/yosys: Update to 0.8

PR:		233077
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D17642
09 Nov 2018 19:18:35
Original commit files touched by this commit  0.7.783
Revision:484538
swills search for other commits by this committer
devel/yosys: use simpler way of dealing with compiler issues

PR:		232117
Submitted by:	jbeich
Pointyhat to:	swills
09 Nov 2018 17:31:57
Original commit files touched by this commit  0.7.783
Revision:484532
swills search for other commits by this committer
devel/yosys: fix build with GCC-based architectures

PR:		232650
Submitted by:	Piotr Kubaj <pkubaj@anongoth.pl>
Approved by:	maintainer timeout (jsorocil@gmail.com, >2 weeks)
18 Sep 2018 11:01:51
Original commit files touched by this commit  0.7.783
Revision:480010
linimon search for other commits by this committer
Mark these ports as broken on powerpc64.

While here, pet portlint.

Approved by:	portmgr (tier-2 blanket)
06 Jun 2018 14:19:51
Original commit files touched by this commit  0.7.783
Revision:471844
tobik search for other commits by this committer
New port: devel/yosys

Yosys is a framework for Verilog RTL synthesis.  It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains.

WWW: http://www.clifford.at/yosys/

PR:		227591
Submitted by:	Johnny Sorocil <jsorocil@gmail.com>
Differential Revision:	https://reviews.freebsd.org/D15632

Number of commits found: 8

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