Ports marked with a ^* actually reside within another category but have cad listed as a secondary category.

verilator Synthesizable Verilog to C++ compiler

5.010_1 5.010_1Version of this port present on the latest quarterly branch.

Maintainer: yuri@FreeBSD.org

Port Added: 2023-05-21 22:57:07

License: GPLv3

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• verilator>0:cad/verilator