Port details |
- verilator Synthesizable Verilog to C++ compiler
- 5.006 cad
=0 Version of this port present on the latest quarterly branch. - Maintainer: yuri@FreeBSD.org
 - Port Added: 2019-01-17 23:27:28
- Last Update: 2023-01-24 03:57:18
- Commit Hash: 452499a
- License: GPLv3
- Description:
- Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
¦ ¦ ¦ ¦ 
- pkg-plist: as obtained via:
make generate-plist - Dependency lines:
-
- verilator>0:cad/verilator
- To install the port:
- cd /usr/ports/cad/verilator/ && make install clean
- To add the package, run one of these commands:
- pkg install cad/verilator
- pkg install verilator
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.- PKGNAME: verilator
- Flavors: there is no flavor information for this port.
- distinfo:
- TIMESTAMP = 1674527154
SHA256 (verilator-verilator-v5.006_GH0.tar.gz) = eb4ca4157ba854bc78c86173c58e8bd13311984e964006803dd45dc289450cfe
SIZE (verilator-verilator-v5.006_GH0.tar.gz) = 2866281
- Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- autoconf>0 : devel/autoconf
- bash : shells/bash
- ar : devel/binutils
- help2man : misc/help2man
- bison : devel/bison
- gmake>=4.3 : devel/gmake
- python3.9 : lang/python39
- perl5>=5.32.r0<5.33 : lang/perl5.32
- Test dependencies:
-
- python3.9 : lang/python39
- Runtime dependencies:
-
- gmake : devel/gmake
- python3.9 : lang/python39
- perl5>=5.32.r0<5.33 : lang/perl5.32
- Library dependencies:
-
- libsystemc.so : devel/systemc
- This port is required by:
- for Run
-
- cad/cascade-compiler
- Configuration Options:
- ===> The following configuration options are available for verilator-5.006:
INSTALL_DBG_EXECUTABLES=off: Install *_dbg executables
LEAK_CHECKS=off: Disable intentional memory leaks
===> Use 'make config' to modify these settings
- Options name:
- cad_verilator
- USES:
- bison compiler:c++14-lang gmake localbase:ldflags pathfix perl5 python:build,run,test shebangfix tar:tgz
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
|
Commit History - (may be incomplete: for full details, see links to repositories near top of page) |
Commit | Credits | Log message |
5.006 24 Jan 2023 03:57:18
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 5.004 → 5.006
Reported by: portscout |
5.004 27 Dec 2022 07:50:59
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 5.002 -> 5.004
Reported by: portscout |
5.002 30 Oct 2022 19:42:15
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.228 -> 5.002
Reported by: portscout |
4.228 01 Oct 2022 22:16:33
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.226 -> 4.228
Reported by: portscout |
07 Sep 2022 21:58:51
    |
Stefan Eßer (se)  |
Remove WWW entries moved into port Makefiles
Commit b7f05445c00f has added WWW entries to port Makefiles based on
WWW: lines in pkg-descr files.
This commit removes the WWW: lines of moved-over URLs from these
pkg-descr files.
Approved by: portmgr (tcberner) |
4.226 07 Sep 2022 21:10:59
    |
Stefan Eßer (se)  |
Add WWW entries to port Makefiles
It has been common practice to have one or more URLs at the end of the
ports' pkg-descr files, one per line and prefixed with "WWW:". These
URLs should point at a project website or other relevant resources.
Access to these URLs required processing of the pkg-descr files, and
they have often become stale over time. If more than one such URL was
present in a pkg-descr file, only the first one was tarnsfered into
the port INDEX, but for many ports only the last line did contain the
port specific URL to further information.
There have been several proposals to make a project URL available as
a macro in the ports' Makefiles, over time.
(Only the first 15 lines of the commit message are shown above ) |
4.226 01 Sep 2022 20:10:31
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.224 -> 4.226
Reported by: portscout |
4.224 20 Jun 2022 20:57:33
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.222 -> 4.224
Reported by: portscout |
4.222 03 May 2022 23:34:26
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.220 -> 4.222
Reported by: portscout |
4.220 13 Mar 2022 19:53:45
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.218 -> 4.220
Reported by: portscout |
4.218 25 Jan 2022 05:44:21
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.216 -> 4.218 |
4.216 12 Dec 2021 21:52:38
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.214 -> 4.216
Reported by: portscout |
4.214 21 Oct 2021 00:46:01
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.212 -> 4.214
Reported by: portscout |
4.212_1 30 Sep 2021 16:10:42
    |
Yuri Victorovich (yuri)  |
cad/verilator: Use GNU ar from devel/binutils
verilator requires the GNU ar feature: '@' file prefix indicating
that the file contains command-line options.
Reference: https://github.com/verilator/verilator/issues/2999
Reported by: Antonin Houska <ah@melesmeles.cz> |
4.212 13 Sep 2021 22:46:09
    |
Yuri Victorovich (yuri)  |
cad/verilator: Cosmetic fix - use bash as configure shell |
4.212 13 Sep 2021 22:29:00
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.210 -> 4.212
Project doesn't distribute tarballs any more in favor of GitHub
tags. |
4.210_1 25 Aug 2021 20:28:24
    |
Yuri Victorovich (yuri)  |
cad/verilator: Backport the fix of bug that caused wrong C++ code generation |
4.210 03 Aug 2021 08:36:58
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.204 -> 4.210 |
4.204 22 Jun 2021 08:54:47
    |
Yuri Victorovich (yuri)  |
cad/verilator: Broken on i386
Reported by: fallout |
4.204 18 Jun 2021 17:16:57
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.202 -> 4.204 |
4.202_1 07 Jun 2021 20:41:13
    |
Yuri Victorovich (yuri)  |
cad/verilator: Backport of fix of missing #include <array> bug. |
4.202 24 Apr 2021 22:18:59
    |
Yuri Victorovich (yuri)  |
cad/verilator: Update 4.200 -> 4.202 |
4.200 07 Apr 2021 08:09:01
    |
Mathieu Arnold (mat)  |
One more small cleanup, forgotten yesterday.
Reported by: lwhsu |
4.200 06 Apr 2021 14:31:07
    |
Mathieu Arnold (mat)  |
Remove # $FreeBSD$ from Makefiles. |
4.200 20 Mar 2021 01:29:51
  |
yuri  |
cad/verilator: Update 4.110 -> 4.200 |
4.110 27 Feb 2021 04:19:02
  |
yuri  |
cad/verilator: Update 4.108 -> 4.110 |
4.108 26 Jan 2021 13:59:25
  |
sunpoet  |
Fix build with bison 3.7.4
PR: 248911
Exp-run by: antoine |
4.108 13 Jan 2021 02:00:40
  |
yuri  |
cad/verilator: Update 4.106 -> 4.108 |
4.106 06 Dec 2020 20:23:04
  |
yuri  |
cad/verilator: Update 4.104 -> 4.106 |
4.104 17 Nov 2020 19:35:09
  |
yuri  |
cad/verilator: Update 4.102 -> 4.104 |
4.102 15 Oct 2020 22:11:24
  |
yuri  |
cad/verilator: Update 4.100 -> 4.102 |
4.100_1 16 Sep 2020 04:29:35
  |
yuri  |
cad/verilator: Add the run-tim dependency on gmake |
4.100 15 Sep 2020 06:05:47
  |
yuri  |
cad/verilator: Update 4.040 -> 4.100 |
4.040_2 11 Sep 2020 20:13:57
  |
yuri  |
cad/verilator: Add options INSTALL_DBG_EXECUTABLES and LEAK_CHECKS |
4.040_1 01 Sep 2020 03:14:17
  |
yuri  |
cad/verilator: Add the SystemC dependency
Also:
* Remove unnecessary patch that has been already applied upstream
* Fix BINARY_ALIAS added for testing |
4.040 01 Sep 2020 01:57:59
  |
yuri  |
cad/verilator: Add the 'test' target |
4.040 18 Aug 2020 17:56:39
  |
yuri  |
cad/verilator: Update 4.038 -> 4.040
Taking maintainership based on the maintainer's request.
PR: 248713
Approved by: kevinz5000@gmail.com (maintainer) |
4.038 18 Jul 2020 23:00:44
  |
yuri  |
cad/verilator: Update 4.036 -> 4.038
PR: 248086
Approved by: kevinz5000@gmail.com (maintainer) |
4.036 08 Jul 2020 22:53:00
  |
yuri  |
cad/verilator: Update 4.034 -> 4.036
PR: 247858
Approved by: kevinz5000@gmail.com (maintainer) |
4.034 25 May 2020 18:25:19
  |
sunpoet  |
Fix build with bison 3.6.2 |
4.034 23 May 2020 19:04:30
  |
yuri  |
cad/verilator: Update 4.028 -> 4.034
PR: 243698
Approved by: kevinz5000@gmail.com (maintainer's timeout; 110 days) |
4.028 12 Feb 2020 07:31:51
  |
yuri  |
cad/verilator: Update 4.024 -> 4.028
PR: 244067
Approved by: kevinz5000@gmail.com (maintainer) |
4.024 05 Jan 2020 08:00:43
  |
yuri  |
cad/verilator: Update 4.020 -> 4.024
PR: 243107
Approved by: kevinz5000@gmail.com (maintainer) |
4.020 19 Oct 2019 22:07:56
  |
yuri  |
cad/verilator: Update 4.008 -> 4.020
PR: 241346
Approved by: kevinz5000@gmail.com (maintainer) |
4.008_2 26 Jul 2019 20:46:57
  |
gerald  |
Bump PORTREVISION for ports depending on the canonical version of GCC
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.
PR: 238330 |
4.008_1 13 Mar 2019 05:24:22
  |
linimon  |
Fix build on gcc-based architectures:
configure: error: the c++ compiler appears to not support C++11.
Approved by: portmgr (tier-2 blanket) |
4.008_1 27 Jan 2019 12:34:35
  |
swills  |
cad/verilator: remove unnecessary BUILD_DEPENDS
PR: 235053
Submitted by: John Hein <jcfyecrayz@liamekaens.com>
Approved by: Kevin Zheng <kevinz5000@gmail.com> (maintainer) |
4.008 27 Jan 2019 12:25:32
  |
swills  |
cad/verilator: update to 4.008
PR: 235228
Approved by: kevinz5000@gmail.com (maintainer) |
3.924 17 Jan 2019 23:27:11
  |
swills  |
cad/verilator: create port
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
WWW: https://www.veripool.org/projects/verilator/wiki/Intro
PR: 230761
Submitted by: Kevin Zheng <kevinz5000@gmail.com> |