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Port details
verilator Synthesizable Verilog to C++ compiler
4.008_1 cad on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port
Maintainer: kevinz5000@gmail.com search for ports maintained by this maintainer
Port Added: 2019-01-17 23:27:28
Last Update: 2019-01-27 12:34:35
SVN Revision: 491344
License: GPLv3
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro
SVNWeb : Homepage : PortsMon
    Pseudo-pkg-plist information, but much better, from make generate-plist
    Expand this list (76 items)
  1. /usr/local/share/licenses/verilator-4.008_1/catalog.mk
  2. /usr/local/share/licenses/verilator-4.008_1/LICENSE
  3. /usr/local/share/licenses/verilator-4.008_1/GPLv3
  4. bin/verilator
  5. bin/verilator_bin
  6. bin/verilator_coverage
  7. bin/verilator_gantt
  8. bin/verilator_profcfunc
  9. libdata/pkgconfig/verilator.pc
  10. man/man1/verilator.1.gz
  11. man/man1/verilator_coverage.1.gz
  12. man/man1/verilator_gantt.1.gz
  13. man/man1/verilator_profcfunc.1.gz
  14. share/verilator/bin/verilator_includer
  15. share/verilator/examples/hello_world_c/Makefile
  16. share/verilator/examples/hello_world_c/sim_main.cpp
  17. share/verilator/examples/hello_world_c/top.v
  18. share/verilator/examples/hello_world_sc/Makefile
  19. share/verilator/examples/hello_world_sc/sc_main.cpp
  20. share/verilator/examples/hello_world_sc/top.v
  21. share/verilator/examples/tracing_c/Makefile
  22. share/verilator/examples/tracing_c/Makefile_obj
  23. share/verilator/examples/tracing_c/input.vc
  24. share/verilator/examples/tracing_c/sim_main.cpp
  25. share/verilator/examples/tracing_c/sub.v
  26. share/verilator/examples/tracing_c/top.v
  27. share/verilator/examples/tracing_sc/Makefile
  28. share/verilator/examples/tracing_sc/Makefile_obj
  29. share/verilator/examples/tracing_sc/input.vc
  30. share/verilator/examples/tracing_sc/sc_main.cpp
  31. share/verilator/examples/tracing_sc/sub.v
  32. share/verilator/examples/tracing_sc/top.v
  33. share/verilator/include/gtkwave/fastlz.c
  34. share/verilator/include/gtkwave/fastlz.h
  35. share/verilator/include/gtkwave/fst_config.h
  36. share/verilator/include/gtkwave/fstapi.c
  37. share/verilator/include/gtkwave/fstapi.h
  38. share/verilator/include/gtkwave/lxt2_write.cpp
  39. share/verilator/include/gtkwave/lxt2_write.h
  40. share/verilator/include/gtkwave/lz4.c
  41. share/verilator/include/gtkwave/lz4.h
  42. share/verilator/include/gtkwave/wavealloca.h
  43. share/verilator/include/verilated.cpp
  44. share/verilator/include/verilated.h
  45. share/verilator/include/verilated.mk
  46. share/verilator/include/verilated.v
  47. share/verilator/include/verilated_config.h
  48. share/verilator/include/verilated_config.h.in
  49. share/verilator/include/verilated_cov.cpp
  50. share/verilator/include/verilated_cov.h
  51. share/verilator/include/verilated_cov_key.h
  52. share/verilator/include/verilated_dpi.cpp
  53. share/verilator/include/verilated_dpi.h
  54. share/verilator/include/verilated_fst_c.cpp
  55. share/verilator/include/verilated_fst_c.h
  56. share/verilator/include/verilated_heavy.h
  57. share/verilator/include/verilated_imp.h
  58. share/verilator/include/verilated_lxt2_c.cpp
  59. share/verilator/include/verilated_lxt2_c.h
  60. share/verilator/include/verilated_save.cpp
  61. share/verilator/include/verilated_save.h
  62. share/verilator/include/verilated_sc.h
  63. share/verilator/include/verilated_sym_props.h
  64. share/verilator/include/verilated_syms.h
  65. share/verilator/include/verilated_threads.cpp
  66. share/verilator/include/verilated_threads.h
  67. share/verilator/include/verilated_unordered_set_map.h
  68. share/verilator/include/verilated_vcd_c.cpp
  69. share/verilator/include/verilated_vcd_c.h
  70. share/verilator/include/verilated_vcd_sc.cpp
  71. share/verilator/include/verilated_vcd_sc.h
  72. share/verilator/include/verilated_vpi.cpp
  73. share/verilator/include/verilated_vpi.h
  74. share/verilator/include/verilatedos.h
  75. share/verilator/include/vltstd/svdpi.h
  76. share/verilator/include/vltstd/vpi_user.h
  77. Collapse this list.

Dependency line: verilator>0:cad/verilator


To install the port: cd /usr/ports/cad/verilator/ && make install clean
To add the package: pkg install verilator

PKGNAME: verilator

There is no flavor information for this port.

distinfo:

TIMESTAMP = 1548558502
SHA256 (verilator-4.008.tgz) = d5cef6edd3bdb7754776d902daae7a7e5dd662baa7c7f895cb7028b1d6910cac
SIZE (verilator-4.008.tgz) = 2519234


NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.

Build dependencies:
  1. bison : devel/bison
  2. gmake : devel/gmake
  3. perl5>=5.28.r1<5.29 : lang/perl5.28
Runtime dependencies:
  1. perl5>=5.28.r1<5.29 : lang/perl5.28
There are no ports dependent upon this port

Configuration Options
     No options to configure

USES:
bison gmake pathfix perl5 tar:tgz

Master Sites:
  1. https://www.veripool.org/ftp/

Number of commits found: 3

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
27 Jan 2019 12:34:35
Original commit files touched by this commit  4.008_1
Revision:491344
swills search for other commits by this committer
cad/verilator: remove unnecessary BUILD_DEPENDS

PR:		235053
Submitted by:	John Hein <jcfyecrayz@liamekaens.com>
Approved by:	Kevin Zheng <kevinz5000@gmail.com> (maintainer)
27 Jan 2019 12:25:32
Original commit files touched by this commit  4.008
Revision:491343
swills search for other commits by this committer
cad/verilator: update to 4.008

PR:		235228
Approved by:	kevinz5000@gmail.com (maintainer)
17 Jan 2019 23:27:11
Original commit files touched by this commit  3.924
Revision:490609
swills search for other commits by this committer
cad/verilator: create port

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

PR:		230761
Submitted by:	Kevin Zheng <kevinz5000@gmail.com>

Number of commits found: 3

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