| Commit History - (may be incomplete: see SVNWeb link above for full details) |
| Date | By | Description |
12 Feb 2020 07:31:51
  4.028
|
yuri  |
cad/verilator: Update 4.024 -> 4.028
PR: 244067
Approved by: kevinz5000@gmail.com (maintainer) |
05 Jan 2020 08:00:43
4.024
|
yuri |
cad/verilator: Update 4.020 -> 4.024
PR: 243107
Approved by: kevinz5000@gmail.com (maintainer) |
19 Oct 2019 22:07:56
4.020
|
yuri |
cad/verilator: Update 4.008 -> 4.020
PR: 241346
Approved by: kevinz5000@gmail.com (maintainer) |
26 Jul 2019 20:46:57
4.008_2
|
gerald |
Bump PORTREVISION for ports depending on the canonical version of GCC
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.
This includes ports
- with USE_GCC=yes or USE_GCC=any,
- with USES=fortran,
- using Mk/bsd.octave.mk which in turn features USES=fortran, and
- with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.
PR: 238330 |
13 Mar 2019 05:24:22
4.008_1
|
linimon |
Fix build on gcc-based architectures:
configure: error: the c++ compiler appears to not support C++11.
Approved by: portmgr (tier-2 blanket) |
27 Jan 2019 12:34:35
4.008_1
|
swills |
cad/verilator: remove unnecessary BUILD_DEPENDS
PR: 235053
Submitted by: John Hein <jcfyecrayz@liamekaens.com>
Approved by: Kevin Zheng <kevinz5000@gmail.com> (maintainer) |
27 Jan 2019 12:25:32
4.008
|
swills |
cad/verilator: update to 4.008
PR: 235228
Approved by: kevinz5000@gmail.com (maintainer) |
17 Jan 2019 23:27:11
3.924
|
swills |
cad/verilator: create port
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
WWW: https://www.veripool.org/projects/verilator/wiki/Intro
PR: 230761
Submitted by: Kevin Zheng <kevinz5000@gmail.com> |
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