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Port details
verilator Synthesizable Verilog to C++ compiler
4.028 cad on this many watch lists=0 search for ports that depend on this port Find issues related to this port Report an issue related to this port 4.028Version of this port present on the latest quarterly branch.
Maintainer: kevinz5000@gmail.com search for ports maintained by this maintainer
Port Added: 2019-01-17 23:27:28
Last Update: 2020-02-12 07:31:51
SVN Revision: 525899
License: GPLv3
Description:
SVNWeb : Homepage
pkg-plist: as obtained via: make generate-plist
Expand this list (88 items)
  1. /usr/local/share/licenses/verilator-4.028/catalog.mk
  2. /usr/local/share/licenses/verilator-4.028/LICENSE
  3. /usr/local/share/licenses/verilator-4.028/GPLv3
  4. bin/verilator
  5. bin/verilator_bin
  6. bin/verilator_coverage
  7. bin/verilator_gantt
  8. bin/verilator_profcfunc
  9. libdata/pkgconfig/verilator.pc
  10. man/man1/verilator.1.gz
  11. man/man1/verilator_coverage.1.gz
  12. man/man1/verilator_gantt.1.gz
  13. man/man1/verilator_profcfunc.1.gz
  14. share/verilator/bin/verilator_includer
  15. share/verilator/examples/cmake_hello_c/CMakeLists.txt
  16. share/verilator/examples/cmake_hello_c/Makefile
  17. share/verilator/examples/cmake_hello_sc/CMakeLists.txt
  18. share/verilator/examples/cmake_hello_sc/Makefile
  19. share/verilator/examples/cmake_protect_lib/CMakeLists.txt
  20. share/verilator/examples/cmake_protect_lib/Makefile
  21. share/verilator/examples/cmake_tracing_c/CMakeLists.txt
  22. share/verilator/examples/cmake_tracing_c/Makefile
  23. share/verilator/examples/cmake_tracing_sc/CMakeLists.txt
  24. share/verilator/examples/cmake_tracing_sc/Makefile
  25. share/verilator/examples/make_hello_c/Makefile
  26. share/verilator/examples/make_hello_c/sim_main.cpp
  27. share/verilator/examples/make_hello_c/top.v
  28. share/verilator/examples/make_hello_sc/Makefile
  29. share/verilator/examples/make_hello_sc/sc_main.cpp
  30. share/verilator/examples/make_hello_sc/top.v
  31. share/verilator/examples/make_protect_lib/Makefile
  32. share/verilator/examples/make_protect_lib/secret_impl.v
  33. share/verilator/examples/make_protect_lib/sim_main.cpp
  34. share/verilator/examples/make_protect_lib/top.v
  35. share/verilator/examples/make_tracing_c/Makefile
  36. share/verilator/examples/make_tracing_c/Makefile_obj
  37. share/verilator/examples/make_tracing_c/input.vc
  38. share/verilator/examples/make_tracing_c/sim_main.cpp
  39. share/verilator/examples/make_tracing_c/sub.v
  40. share/verilator/examples/make_tracing_c/top.v
  41. share/verilator/examples/make_tracing_sc/Makefile
  42. share/verilator/examples/make_tracing_sc/Makefile_obj
  43. share/verilator/examples/make_tracing_sc/input.vc
  44. share/verilator/examples/make_tracing_sc/sc_main.cpp
  45. share/verilator/examples/make_tracing_sc/sub.v
  46. share/verilator/examples/make_tracing_sc/top.v
  47. share/verilator/include/gtkwave/fastlz.c
  48. share/verilator/include/gtkwave/fastlz.h
  49. share/verilator/include/gtkwave/fst_config.h
  50. share/verilator/include/gtkwave/fstapi.c
  51. share/verilator/include/gtkwave/fstapi.h
  52. share/verilator/include/gtkwave/lz4.c
  53. share/verilator/include/gtkwave/lz4.h
  54. share/verilator/include/gtkwave/wavealloca.h
  55. share/verilator/include/verilated.cpp
  56. share/verilator/include/verilated.h
  57. share/verilator/include/verilated.mk
  58. share/verilator/include/verilated.v
  59. share/verilator/include/verilated_config.h
  60. share/verilator/include/verilated_config.h.in
  61. share/verilator/include/verilated_cov.cpp
  62. share/verilator/include/verilated_cov.h
  63. share/verilator/include/verilated_cov_key.h
  64. share/verilator/include/verilated_dpi.cpp
  65. share/verilator/include/verilated_dpi.h
  66. share/verilator/include/verilated_fst_c.cpp
  67. share/verilator/include/verilated_fst_c.h
  68. share/verilator/include/verilated_heavy.h
  69. share/verilator/include/verilated_imp.h
  70. share/verilator/include/verilated_save.cpp
  71. share/verilator/include/verilated_save.h
  72. share/verilator/include/verilated_sc.h
  73. share/verilator/include/verilated_sym_props.h
  74. share/verilator/include/verilated_syms.h
  75. share/verilator/include/verilated_threads.cpp
  76. share/verilator/include/verilated_threads.h
  77. share/verilator/include/verilated_unordered_set_map.h
  78. share/verilator/include/verilated_vcd_c.cpp
  79. share/verilator/include/verilated_vcd_c.h
  80. share/verilator/include/verilated_vcd_sc.cpp
  81. share/verilator/include/verilated_vcd_sc.h
  82. share/verilator/include/verilated_vpi.cpp
  83. share/verilator/include/verilated_vpi.h
  84. share/verilator/include/verilatedos.h
  85. share/verilator/include/vltstd/svdpi.h
  86. share/verilator/include/vltstd/vpi_user.h
  87. share/verilator/verilator-config-version.cmake
  88. share/verilator/verilator-config.cmake
Collapse this list.
Dependency lines:
  • verilator>0:cad/verilator
To install the port: cd /usr/ports/cad/verilator/ && make install clean
To add the package: pkg install verilator
PKGNAME: verilator
Flavors: there is no flavor information for this port.
distinfo:

Dependencies
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
Build dependencies:
  1. bison : devel/bison
  2. gmake : devel/gmake
  3. perl5>=5.30.r1<5.31 : lang/perl5.30
Runtime dependencies:
  1. perl5>=5.30.r1<5.31 : lang/perl5.30
This port is required by:
for Run
  1. cad/cascade-compiler

Configuration Options

USES:

Master Sites:
  1. https://www.veripool.org/ftp/

Number of commits found: 8

Commit History - (may be incomplete: see SVNWeb link above for full details)
DateByDescription
12 Feb 2020 07:31:51
Original commit files touched by this commit  4.028
Revision:525899
yuri search for other commits by this committer
cad/verilator: Update 4.024 -> 4.028

PR:		244067
Approved by:	kevinz5000@gmail.com (maintainer)
05 Jan 2020 08:00:43
Original commit files touched by this commit  4.024
Revision:522113
yuri search for other commits by this committer
cad/verilator: Update 4.020 -> 4.024

PR:		243107
Approved by:	kevinz5000@gmail.com (maintainer)
19 Oct 2019 22:07:56
Original commit files touched by this commit  4.020
Revision:514852
yuri search for other commits by this committer
cad/verilator: Update 4.008 -> 4.020

PR:		241346
Approved by:	kevinz5000@gmail.com (maintainer)
26 Jul 2019 20:46:57
Original commit files touched by this commit  4.008_2
Revision:507372
gerald search for other commits by this committer
Bump PORTREVISION for ports depending on the canonical version of GCC
as defined in Mk/bsd.default-versions.mk which has moved from GCC 8.3
to GCC 9.1 under most circumstances now after revision 507371.

This includes ports
 - with USE_GCC=yes or USE_GCC=any,
 - with USES=fortran,
 - using Mk/bsd.octave.mk which in turn features USES=fortran, and
 - with USES=compiler specifying openmp, nestedfct, c11, c++0x, c++11-lang,
   c++11-lib, c++14-lang, c++17-lang, or gcc-c++11-lib
plus, everything INDEX-11 shows with a dependency on lang/gcc9 now.

PR:		238330
13 Mar 2019 05:24:22
Original commit files touched by this commit  4.008_1
Revision:495557
linimon search for other commits by this committer
Fix build on gcc-based architectures:

  configure: error: the c++ compiler appears to not support C++11.

Approved by:	portmgr (tier-2 blanket)
27 Jan 2019 12:34:35
Original commit files touched by this commit  4.008_1
Revision:491344
swills search for other commits by this committer
cad/verilator: remove unnecessary BUILD_DEPENDS

PR:		235053
Submitted by:	John Hein <jcfyecrayz@liamekaens.com>
Approved by:	Kevin Zheng <kevinz5000@gmail.com> (maintainer)
27 Jan 2019 12:25:32
Original commit files touched by this commit  4.008
Revision:491343
swills search for other commits by this committer
cad/verilator: update to 4.008

PR:		235228
Approved by:	kevinz5000@gmail.com (maintainer)
17 Jan 2019 23:27:11
Original commit files touched by this commit  3.924
Revision:490609
swills search for other commits by this committer
cad/verilator: create port

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

PR:		230761
Submitted by:	Kevin Zheng <kevinz5000@gmail.com>

Number of commits found: 8

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