| Port details |
- verilator Synthesizable Verilog to C++ compiler
4.008_1 cad  =0   
- Maintainer: kevinz5000@gmail.com
Port Added: 2019-01-17 23:27:28
Last Update: 2019-01-27 12:34:35
SVN Revision: 491344
License: GPLv3
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
WWW: https://www.veripool.org/projects/verilator/wiki/Intro SVNWeb : Homepage : PortsMon
Dependency line: verilator>0:cad/verilator
To install the port: cd /usr/ports/cad/verilator/ && make install clean
To add the package: pkg install verilator PKGNAME: verilator There is no flavor information for this port. distinfo: TIMESTAMP = 1548558502
SHA256 (verilator-4.008.tgz) = d5cef6edd3bdb7754776d902daae7a7e5dd662baa7c7f895cb7028b1d6910cac
SIZE (verilator-4.008.tgz) = 2519234
NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered. Build dependencies:
- bison : devel/bison
- gmake : devel/gmake
- perl5>=5.28.r1<5.29 : lang/perl5.28
Runtime dependencies:
- perl5>=5.28.r1<5.29 : lang/perl5.28
There are no ports dependent upon this port
Configuration Options
No options to configure
USES:
bison gmake pathfix perl5 tar:tgz
Master Sites:
- https://www.veripool.org/ftp/
|
Number of commits found: 3
| Commit History - (may be incomplete: see SVNWeb link above for full details) |
| Date | By | Description |
27 Jan 2019 12:34:35
  4.008_1
 |
swills |
cad/verilator: remove unnecessary BUILD_DEPENDS
PR: 235053
Submitted by: John Hein <jcfyecrayz@liamekaens.com>
Approved by: Kevin Zheng <kevinz5000@gmail.com> (maintainer) |
27 Jan 2019 12:25:32
4.008
|
swills |
cad/verilator: update to 4.008
PR: 235228
Approved by: kevinz5000@gmail.com (maintainer) |
17 Jan 2019 23:27:11
3.924
|
swills |
cad/verilator: create port
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.
WWW: https://www.veripool.org/projects/verilator/wiki/Intro
PR: 230761
Submitted by: Kevin Zheng <kevinz5000@gmail.com> |
Number of commits found: 3
|
| Latest Vulnerabilities |
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10 vulnerabilities affecting 77 ports have been reported in the past 14 days
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* - modified, not new All vulnerabilities
Last updated:
2019-02-20 10:14:19
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