| Port details on branch 2026Q3 |
- iverilog Verilog simulation and synthesis tool
- 13.0 cad
 =4      13.0Version of this port present on the latest quarterly branch. - Maintainer: kbowling@FreeBSD.org
- Port Added: 2001-02-13 08:02:19
- Last Update: 2026-03-06 18:21:03
- Commit Hash: 373b3ed
- People watching this port, also watch:: zip, unzip, cdrtools, autoconf, rsync
- License: GPLv2
- WWW:
- https://steveicarus.github.io/iverilog/
- Description:
- Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
  ¦  ¦  ¦  ¦ 
- Manual pages:
-
- pkg-plist: as obtained via:
make generate-plist - USE_RC_SUBR (Service Scripts)
- no SUBR information found for this port
- Dependency lines:
-
- To install the port:
- cd /usr/ports/cad/iverilog/ && make install clean
- To add the package, run one of these commands:
- pkg install cad/iverilog
- pkg install iverilog
NOTE: If this package has multiple flavors (see below), then use one of them instead of the name specified above.- PKGNAME: iverilog
- Flavors: there is no flavor information for this port.
- distinfo:
- TIMESTAMP = 1772820908
SHA256 (steveicarus-iverilog-13.0-v13_0_GH0.tar.gz) = c897bbfa9848688982c6d5c30529fc29d68df0b9ff22ffa73bad89db73a7ce49
SIZE (steveicarus-iverilog-13.0-v13_0_GH0.tar.gz) = 3215392
Packages (timestamps in pop-ups are UTC):
- Dependencies
- NOTE: FreshPorts displays only information on required and default dependencies. Optional dependencies are not covered.
- Build dependencies:
-
- gperf : devel/gperf
- bison : devel/bison
- gmake>=4.4.1 : devel/gmake
- Library dependencies:
-
- libreadline.so.8 : devel/readline
- This port is required by:
- for Run
-
- cad/py-cocotb
- java/veditor
Configuration Options:- No options to configure
- Options name:
- cad_iverilog
- USES:
- bison compiler:c++11-lang gmake readline
- FreshPorts was unable to extract/find any pkg message
- Master Sites:
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