Ports marked with a ^* actually reside within another category but have cad listed as a secondary category.

klayout Qt-based chip mask layout viewing and editing tool

0.30.9 0.30.9Version of this port present on the latest quarterly branch.

Maintainer: kevinz5000@gmail.com

Port Added: 2026-07-27 21:44:22

License: GPLv2

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• klayout>0:cad/klayout

py-cocotb Coroutine based cosimulation library for writing VHDL and Verilog

2.0.1 2.0.1Version of this port present on the latest quarterly branch.

Maintainer: yuri@FreeBSD.org

Port Added: 2026-07-29 01:03:11

Also Listed In: python

License: BSD3CLAUSE

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• ${PYTHON_PKGNAMEPREFIX}cocotb>0:cad/py-cocotb@${PY_FLAVOR}

py-gmsh Automatic 3D finite element mesh generator (gmsh's own binding)

4.14.0_1 4.14.0_1Version of this port present on the latest quarterly branch.

Maintainer: yuri@FreeBSD.org

Port Added: 2026-07-13 16:24:08

Also Listed In: python

License: AGPLv3+ APACHE20 GPLv3+ GPLv2+ LGPL21

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• ${PYTHON_PKGNAMEPREFIX}gmsh>0:cad/py-gmsh@${PY_FLAVOR}

qspeakers Open source loudspeaker enclosure designer

1.8.6 1.8.6Version of this port present on the latest quarterly branch.

Maintainer: riggs@FreeBSD.org

Port Added: 2026-07-11 13:33:04

License: GPLv3

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• qspeakers>0:cad/qspeakers

tochnog Free explicit/implicit Finite Element Program

20140100_15 20140100_15Version of this port present on the latest quarterly branch.

There is no maintainer for this port.

Any concerns regarding this port should be directed to the FreeBSD Ports mailing list via ports@FreeBSD.org

Port Added: 2026-07-15 20:48:08

License: GPLv2

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• tochnog>0:cad/tochnog

verilator Synthesizable Verilog to C++ compiler

5.050_2 5.050_2Version of this port present on the latest quarterly branch.

Maintainer: yuri@FreeBSD.org

Port Added: 2026-07-14 01:09:06

License: ART20 LGPL3+

USE_RC_SUBR (Service Scripts)

• no SUBR information found for this port

Dependency lines:

• verilator>0:cad/verilator